Three-dimensional memory structure having a back gate electrode

ABSTRACT

A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.

RELATED APPLICATIONS

The present application is related to a copending application serialnumber 14/______ (Attorney Docket No. 3590-491B), of which the entirecontent is incorporated herein by reference.

FIELD

The present disclosure relates generally to the field of semiconductordevices and specifically to three-dimensional memory structures, such asvertical NAND strings, that include a back gate electrode, and methodsof making thereof.

BACKGROUND

Three-dimensional vertical NAND strings having one bit per cell aredisclosed in an article by T. Endoh, et. al., titled “Novel Ultra HighDensity Memory With A Stacked-Surrounding Gate Transistor (S-SGT)Structured Cell”, IEDM Proc. (2001) 33-36.

SUMMARY

According to an aspect of the present disclosure, a monolithicthree-dimensional memory structure is provided, which comprises a stackincluding an alternating plurality of insulator layers and electricallyconductive layers, a trench extending through the stack and including afirst sidewall and a second sidewall that are laterally spaced from eachother, and a plurality of semiconductor strip structures straddling thetrench. Each semiconductor strip structure contacts a respective portionof the first sidewall and a respective portion of the second sidewalland is laterally spaced from one another. The monolithicthree-dimensional memory structure further comprises a back gatedielectric contacting inner sidewalls of the plurality of semiconductorstrip structures, and a back gate electrode contacting inner sidewallsof the back gate dielectric.

According to another aspect of the present disclosure, a monolithicthree-dimensional memory structure is provided, which comprises a stackincluding an alternating plurality of insulator layers and electricallyconductive layers, a memory opening extending through the stack, and apillar structure located within the memory opening and comprising a backgate electrode and a set of nested layers laterally surrounding the backgate electrode. The set of nested layers include, from inside tooutside, a back gate dielectric, a semiconductor channel, and a memoryfilm.

According to yet another aspect of the present disclosure, a method ofmanufacturing a monolithic three-dimensional memory structure isprovided. A stack including an alternating plurality of first materiallayers and second material layers is formed over a substrate. A trenchis formed, which vertically extends through the stack and laterallyextends along a first horizontal direction. A plurality of semiconductorstrip structures is formed, which straddles the trench and extends alonga second horizontal direction that is different from the firsthorizontal direction. A back gate dielectric is formed on innersidewalls of the plurality of semiconductor strip structures. A backgate electrode is formed on inner sidewalls of the back gate dielectric.

According to still another aspect of the present disclosure, a method ofmanufacturing a monolithic three-dimensional memory structure isprovided. A stack including an alternating plurality of first materiallayers and second material layers is formed over a substrate. A memoryopening is formed, which extends through the stack. A memory film isformed on a sidewall of the memory opening. A semiconductor channel isformed on the memory film within the memory opening. The semiconductorchannel is electrically isolated from the substrate by the memory film.A back gate dielectric is formed on the semiconductor channel within thememory opening. A back gate electrode is formed on the back gatedielectric and within the memory opening.

According to another aspect of the present disclosure, a method ofoperating a three-dimensional memory device is provided. Athree-dimensional memory device is provided, which comprises a stackincluding an alternating plurality of insulator layers and electricallyconductive layers that include control gate electrodes located at theirrespective level, a plurality of charge storage elements located in thestack, a semiconductor channel located on a first side of the pluralityof charge storage elements and within the stack, and a back gateelectrode located on a second side of the plurality of charge storageelements and within the stack. A set of at least one charge storageelement located at a selected level of the stack is programmed byinjecting electrical charges into the set of at least one charge storageelement. The total amount of electrical charge stored within the set ofat least one charge storage element is a function of the selected modeof programming that is selected from among a plurality of modes ofprogramming Electrical current through the semiconductor channel can bemeasured under a plurality of electrical bias conditions. Each of theplurality of electrical bias conditions differs from one another by atleast one of a value for a backside bias voltage applied to the backgate electrode and a value for a control gate bias voltage applied to acontrol gate electrode located at the selected level. A subset ofelectrical bias conditions under which a respective measured electricalcurrent through the semiconductor channel is below a predefinedthreshold level is identified. A total amount of electrical chargestored in the set of at least one charge storage element is determinedbased on the identified subset of electrical bias conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective view of a first exemplary structure afterformation of a stack of alternating plurality of material layersaccording to a first embodiment of the present disclosure.

FIG. 1B is a vertical cross-sectional view of the first exemplarystructure of FIG. 1A.

FIG. 2A is a perspective view of the first exemplary structure afterformation of electrically insulating portions according to the firstembodiment of the present disclosure.

FIG. 2B is a vertical cross-sectional view of the first exemplarystructure of FIG. 2A.

FIG. 3A is a perspective view of the first exemplary structure afterformation of line trenches according to the first embodiment of thepresent disclosure.

FIG. 3B is a vertical cross-sectional view of the first exemplarystructure of FIG. 3A.

FIG. 4A is a perspective view of the first exemplary structure afterformation of a blocking dielectric layer, a tunneling dielectric layer,and a semiconductor material layer according to the first embodiment ofthe present disclosure.

FIG. 4B is a vertical cross-sectional view of the first exemplarystructure of FIG. 4A.

FIG. 5A is a perspective view of the first exemplary structure afterformation of a first dielectric cap material layer according to thefirst embodiment of the present disclosure.

FIG. 5B is a vertical cross-sectional view of the first exemplarystructure of FIG. 5A.

FIG. 6A is a perspective view of the first exemplary structure afterpatterning the first dielectric cap material layer and the semiconductormaterial layer according to the first embodiment of the presentdisclosure.

FIG. 6B is a vertical cross-sectional view of the first exemplarystructure of FIG. 6A.

FIG. 7A is a perspective view of the first exemplary structure afterformation of a second dielectric cap material layer according to thefirst embodiment of the present disclosure.

FIG. 7B is a vertical cross-sectional view of the first exemplarystructure of FIG. 7A.

FIG. 8A is a perspective view of the first exemplary structure afterformation of line cavities according to the first embodiment of thepresent disclosure.

FIG. 8B is a vertical cross-sectional view of the first exemplarystructure of FIG. 8A.

FIG. 9A is a perspective view of the first exemplary structure afterformation of a back gate dielectric and back gate electrodes accordingto the first embodiment of the present disclosure.

FIG. 9B is a vertical cross-sectional view of the first exemplarystructure of FIG. 9A.

FIG. 10A is a perspective view of a second exemplary structure afterformation of a stack of alternating plurality of material layersaccording to a second embodiment of the present disclosure.

FIG. 10B is a vertical cross-sectional view of the second exemplarystructure of FIG. 1A.

FIG. 11A is a perspective view of the second exemplary structure afterformation of electrically insulating portions according to the secondembodiment of the present disclosure.

FIG. 11B is a vertical cross-sectional view of the second exemplarystructure of FIG. 11A.

FIG. 12A is a perspective view of the second exemplary structure afterformation of line trenches according to the second embodiment of thepresent disclosure.

FIG. 12B is a vertical cross-sectional view of the second exemplarystructure of FIG. 12A.

FIG. 13A is a perspective view of the second exemplary structure afterformation of a blocking dielectric layer, a tunneling dielectric layer,and a semiconductor material layer according to the second embodiment ofthe present disclosure.

FIG. 13B is a vertical cross-sectional view of the second exemplarystructure of FIG. 13A.

FIG. 14A is a perspective view of the second exemplary structure afterformation of a first dielectric cap material layer according to thesecond embodiment of the present disclosure.

FIG. 14B is a vertical cross-sectional view of the second exemplarystructure of FIG. 14A.

FIG. 15A is a perspective view of the second exemplary structure afterpatterning the first dielectric cap material layer and the semiconductormaterial layer according to the second embodiment of the presentdisclosure.

FIG. 15B is a vertical cross-sectional view of the second exemplarystructure of FIG. 15A.

FIG. 16A is a perspective view of the second exemplary structure afterformation of a second dielectric cap material layer according to thesecond embodiment of the present disclosure.

FIG. 16B is a vertical cross-sectional view of the second exemplarystructure of FIG. 16A.

FIG. 17A is a perspective view of the second exemplary structure afterformation of line cavities according to the second embodiment of thepresent disclosure.

FIG. 17B is a vertical cross-sectional view of the second exemplarystructure of FIG. 17A.

FIG. 18A is a perspective view of the second exemplary structure afterformation of a back gate dielectric and back gate electrodes accordingto the second embodiment of the present disclosure.

FIG. 18B is a vertical cross-sectional view of the second exemplarystructure of FIG. 18A.

FIG. 19 is a vertical cross-sectional view of a third exemplarystructure after formation of a stack including an alternating pluralityof material layers according to a third embodiment of the presentdisclosure.

FIG. 20 is a vertical cross-sectional view of the third exemplarystructure after formation of memory openings through the stack accordingto the third embodiment of the present disclosure.

FIG. 21 is a vertical cross-sectional view of the third exemplarystructure after formation of blocking dielectric layers andsemiconductor channels according to the third embodiment of the presentdisclosure.

FIG. 22 is a vertical cross-sectional view of the third exemplarystructure after formation of back gate dielectrics according to thethird embodiment of the present disclosure.

FIG. 23 is a vertical cross-sectional view of the third exemplarystructure after formation of back gate electrodes and a dielectric caplayer according to the third embodiment of the present disclosure.

FIG. 24 is a vertical cross-sectional view of the third exemplarystructure after formation of a backside cavity according to the thirdembodiment of the present disclosure.

FIG. 25 is a vertical cross-sectional view of the third exemplarystructure after replacement of sacrificial material layers withelectrically conductive layers according to the third embodiment of thepresent disclosure.

FIG. 26 is a vertical cross-sectional view of the third exemplarystructure after formation of a backside via spacer according to thethird embodiment of the present disclosure.

FIG. 27 is a vertical cross-sectional view of the third exemplarystructure after formation of a source-level cavity according to thethird embodiment of the present disclosure.

FIG. 28 is a vertical cross-sectional view of the third exemplarystructure after formation of source regions according to the thirdembodiment of the present disclosure.

FIG. 29A is a vertical cross-sectional view of the third exemplarystructure after formation of a source electrode and a backside contactvia structure according to the third embodiment of the presentdisclosure.

FIG. 29B is a horizontal cross-sectional view of the third exemplarystructure of FIG. 29A along the plane B-B′. The vertical plane A-A′corresponds to the vertical plane of the vertical cross-sectional viewof FIG. 29A.

FIG. 30A is a vertical cross-sectional view of the third exemplarystructure after formation of contact via structures and conductive linestructures according to the third embodiment of the present disclosure.

FIG. 30B is another vertical cross-sectional view of the third exemplarystructure of FIG. 30A along a vertical plane that is perpendicular tothe vertical cross-sectional plane of FIG. 30A.

FIG. 31 is a vertical cross-sectional view of an alternate embodiment ofthe third exemplary structure according to the third embodiment of thepresent disclosure.

FIG. 32 is a circuit schematic for an exemplary three-dimensional memorydevice of the present disclosure.

FIG. 33 is a schematic vertical cross-sectional diagram illustrating amechanism for detection of a threshold bias condition according to anembodiment of the present disclosure.

FIG. 34 is a graph illustrating a set of bias voltage conditions thatcan be employed to determine the total amount of stored electricalcharge in a set of at least one memory element at a level within amemory stack structure.

FIG. 35 is a graph illustrating the interdependency for optimal valuesfor the backside bias voltage and unselect control gate bias voltageaccording to an embodiment of the present disclosure.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed tothree-dimensional memory structures, such as vertical NAND strings, thatinclude a back gate electrode, and methods of making thereof, thevarious aspects of which are described below. The embodiments of thedisclosure can be employed to form various structures including amultilevel metal interconnect structure, a non-limiting example of whichincludes semiconductor devices such as three-dimensional monolithicmemory array devices comprising a plurality of NAND memory strings. Thedrawings are not drawn to scale. Multiple instances of an element may beduplicated where a single instance of the element is illustrated, unlessabsence of duplication of elements is expressly described or clearlyindicated otherwise. Ordinals such as “first,” “second,” and “third” areemployed merely to identify similar elements, and different ordinals maybe employed across the specification and the claims of the instantdisclosure. As used herein, a first element located “on” a secondelement can be located on the exterior side of a surface of the secondelement or on the interior side of the second element. As used herein, afirst element is located “directly on” a second element if there exist aphysical contact between a surface of the first element and a surface ofthe second element.

A monolithic three dimensional memory array is one in which multiplememory levels are formed above a single substrate, such as asemiconductor wafer, with no intervening substrates. The term“monolithic” means that layers of each level of the array are directlydeposited on the layers of each underlying level of the array. Incontrast, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic memory device. For example,non-monolithic stacked memories have been constructed by forming memorylevels on separate substrates and vertically stacking the memory levels,as described in U.S. Pat. No. 5,915,167 titled “Three DimensionalStructure Memory.” The substrates may be thinned or removed from thememory levels before bonding, but as the memory levels are initiallyformed over separate substrates, such memories are not true monolithicthree dimensional memory arrays. The various three dimensional memorydevices of the present disclosure include a monolithic three-dimensionalNAND string memory device, and can be fabricated employing the variousembodiments described herein.

Referring to FIG. 1, a first exemplary structure according to anembodiment of the present disclosure is illustrated, which can beemployed, for example, to fabricate a device structure containingvertical NAND memory devices. The exemplary structure includes asubstrate 10, which can be a semiconductor substrate. The substrate caninclude a substrate semiconductor layer, and can include at least oneelemental semiconductor material, at least one III-V compoundsemiconductor material, at least one II-VI compound semiconductormaterial, at least one organic semiconductor material, or othersemiconductor materials known in the art. The substrate can have a majorsurface, which can be, for example, a topmost surface of thesemiconductor material layer. The major surface can be a semiconductorsurface. In one embodiment, the major surface can be a singlecrystalline semiconductor surface.

As used herein, a “semiconductor material” refers to a material havingelectrical conductivity in the range from 1.0×10⁻⁶ S/cm to 1.0×10⁵ S/cm,and is capable of producing a doped material having electricalresistivity in a range from 1.0 S/cm to 1.0×10⁵ S/cm upon suitabledoping with an electrical dopant. As used herein, an “electrical dopant”refers to a p-type dopant that adds a hole to a balance band within aband structure, or an n-type dopant that adds an electron to aconduction band within a band structure. As used herein, a “conductivematerial” refers to a material having electrical conductivity greaterthan 1.0×10⁵ S/cm. As used herein, an “insulator material” or a“dielectric material” refers to a material having electricalconductivity less than 1.0×10⁻⁶ S/cm. All measurements for electricalconductivities are made at the standard condition. Optionally, at leastone doped well (not expressly shown) can be formed within the substratesemiconductor layer 9.

At least one semiconductor device (not shown) for a peripheral circuitrycan be formed on a portion of the substrate semiconductor layer. The atleast one semiconductor device can include, for example, field effecttransistors. For example, at least one dielectric material portion canbe formed by etching portions of the semiconductor material layer anddepositing a dielectric material therein. Optionally, a dielectric padlayer (not shown) can be formed above the semiconductor material layer.Optionally, a lower select gate device level may be fabricated asdescribed in U.S. patent application Ser. No. 14/133,979, filed on Dec.19, 2013, U.S. patent application Ser. No. 14/225,116, filed on Mar. 25,2014, and/or U.S. patent application Ser. No. 14/225,176, filed on Mar.25, 2014, all of which are incorporated herein by reference. Adielectric cap layer (not shown) can be optionally formed.

A stack of an alternating plurality of first material layers 32 andsecond material layers 142 is formed over the top surface of thesubstrate, which can be, for example, on the top surface of thedielectric cap layer 31. As used herein, an alternating plurality offirst elements and second elements refers to a structure in whichinstances of the first elements and instances of the second elementsalternate. Each instance of the first elements that is not an endelement of the alternating plurality is adjoined by two instances of thesecond elements on both sides, and each instance of the second elementsthat is not an end element of the alternating plurality is adjoined bytwo instances of the first elements on both ends. The first elements mayhave the same thickness there amongst, or may have differentthicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. The alternating plurality offirst material layers and second material layers may begin with aninstance of the first material layers or with an instance of the secondmaterial layers. In one embodiment, the alternating plurality of firstmaterial layers and second material layers may end with an instance ofthe first material layers. In one embodiment, an instance of the firstelements and an instance of the second elements may form a unit that isrepeated with periodicity within the alternating plurality.

Each first material layer includes a first material, and each secondmaterial layer includes a second material that is different from thefirst material. In one embodiment, each first material layer 32 can bean insulator layer, and each second material layer 142 can be asacrificial material layer. In this case, the stack can include analternating plurality of first material layers 32 and second materiallayers 142.

The stack of the alternating plurality is herein referred to as analternating stack (32, 142). Each first material layer 32 can becomposed of the first material, and each second material layer 142 canbe composed a second material different from the first material. Thefirst material of the first material layers 32 can be at least oneelectrically insulating material. In other words, the first material canbe an insulator material, and each first material layer 32 can be aninsulator layer. As such, each first material layer 32 can be anelectrically insulating material layer. Electrically insulatingmaterials that can be employed for the first material layers 32 include,but are not limited to, silicon oxide (including doped or undopedsilicate glass), silicon nitride, silicon oxynitride, organosilicateglass (OSG), spin-on dielectric materials, dielectric metal oxides thatare commonly known as high dielectric constant (high-k) dielectricoxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicatesthereof, dielectric metal oxynitrides and silicates thereof, and organicinsulating materials. In one embodiment, the first material of the firstmaterial layers 32 can be silicon oxide.

In one embodiment, the second material of the second material layers 142is a sacrificial material that can be removed selective to the firstmaterial of the first material layers 32. As used herein, a removal of afirst material is “selective to” a second material if the removalprocess removes the first material at a rate that is at least twice therate of removal of the second material. The ratio of the rate of removalof the first material to the rate of removal of the second material isherein referred to as a “selectivity” of the removal process for thefirst material with respect to the second material.

In this case, the second material layers 142 may comprise anelectrically insulating material, a semiconductor material, or aconductive material. The second material of the second material layers142 can be subsequently replaced with electrically conductive electrodeswhich can function, for example, as control gate electrodes of avertical NAND device. Non-limiting examples of the second materialinclude silicon nitride, an amorphous semiconductor material (such asamorphous silicon), and a polycrystalline semiconductor material (suchas polysilicon). In one embodiment, the second material layers 142 canbe material layers that comprise silicon nitride or a semiconductormaterial including at least one of silicon and germanium.

In one embodiment, the first material layers 32 can include siliconoxide, and sacrificial material layers can include silicon nitridesacrificial material layers. The first material of the first materiallayers 32 can be deposited, for example, by chemical vapor deposition(CVD). For example, if silicon oxide is employed for the first materiallayers 32, tetraethyl orthosilicate (TEOS) can be employed as theprecursor material for the CVD process. The second material of thesecond material layers 142 can be formed, for example, CVD or atomiclayer deposition (ALD).

Alternatively, the second material of the second material layers 142 isa permanent conductive material, i.e., a conductive material that is notsubsequently replaced with any other material. In this case, the secondmaterial layers 142 can be conductive material layers. Exemplaryconductive materials that can be employed as the second materialinclude, but are not limited to, a conductive metallic nitride material(such as TiN, TaN, and WN), an elemental metal or an alloy thereof (suchas W, Cu, Al, and alloys thereof), a doped semiconductor material, or acombination thereof.

The second material layers 142 can be suitably patterned so thatconductive material portions that are immediately formed (in case thesecond material layers 142 are conductive material layers), or to besubsequently formed (by replacement of the sacrificial material of thesecond material layers 142 with a conductive material) can function aselectrically conductive electrodes, such as the control gate electrodesof the monolithic three-dimensional NAND string memory devices to besubsequently formed. The second material layers 142 may comprise aportion having a strip shape extending substantially parallel to themajor surface of the substrate.

The thicknesses of the first material layers 32 and the second materiallayers 142 can be in a range from 20 nm to 50 nm, although lesser andgreater thicknesses can be employed for each first material layer 32 andfor each second material layer 142. The number of repetitions of thepairs of a first material layer 32 and a sacrificial material layer(e.g., a control gate electrode or a sacrificial material layer) 142 canbe in a range from 2 to 1,024, and typically from 8 to 256, although agreater number of repetitions can also be employed. The top and bottomgate electrodes in the stack may function as the select gate electrodes.In one embodiment, each second material layer 142 in the alternatingstack (32, 142) can have a uniform thickness that is substantiallyinvariant within each respective second material layer 142.

Referring to FIGS. 2A and 2B, at least one trench can be formed througha set of at least one second material layer 142 located at a top portionof the alternating stack (32, 142). The set of the at least one secondmaterial layer 142 corresponds to at least one level in which drainselect gate electrodes are to be subsequently formed. The total numberof levels within the set of at least one second material layer 142through which the at least one trench is formed can be the same as thenumber of levels within which the drain select gate electrodes are to besubsequently formed. Each of the at least one trench is filled with adielectric material such as silicon oxide or a dielectric metal oxide toform a trench isolation structure 34.

Referring to FIGS. 3A and 3B, a lithographic material stack (not shown)including at least a photoresist layer can be formed over thealternating stack (32, 142), and can be lithographically patterned toform openings therein. The pattern of the opening can include shapesthat extend farther along a first horizontal direction than along asecond horizontal direction that is perpendicular to the firsthorizontal direction. In one embodiment, the pattern can be a periodicpattern that is repeated along at least one direction. The horizontaldirection along which an opening in the photoresist layer extendsfarthest is herein referred to as the lengthwise direction of theopening. As used herein, a “lengthwise direction” of an element is ahorizontal direction along which the element extends the farthest. A“widthwise” direction of an element is a horizontal direction alongwhich the element extends the least. In one embodiment, the widthwisedirection of each opening can be perpendicular to the lengthwisedirection of the opening.

In one embodiment, the pattern of the opening in the photoresist layercan include rectangular shapes. In one embodiment, each opening canextend along a same lengthwise direction, and can have a uniform widthalong a same widthwise direction. As used herein, a “uniform” widthrefers to a width that is invariant under translation along thelengthwise direction. In one embodiment, the pattern of the openings inthe photoresist layer can be a periodic pattern of lines that extendalong the lengthwise direction and having a same uniform width, andhaving a uniform spacing along the widthwise direction.

The pattern in the lithographic material stack can be transferredthrough the entirety of the alternating stack (32, 142) by at least oneanisotropic etch that employs the patterned lithographic material stackas an etch mask. Portions of the alternating stack (32, 142) underlyingthe openings in the patterned lithographic material stack are etched toform trenches that extend along a same lengthwise direction. Thetrenches are herein referred to as line trenches 49. As used herein, aline trench refers to a trench comprising at least one region in which apair of sidewalls are parallel to each other and laterally extend alongthe direction of the sidewalls for a greater distance than the width ofthe respective region.

The transfer of the pattern in the patterned lithographic material stackthrough the alternating stack (32, 142) forms the line trenches 149 thatvertically extend through the alternating stack (32, 142). The chemistryof the anisotropic etch process employed to etch through the materialsof the alternating stack (32, 142) can alternate to optimize etching ofthe first and second materials in the alternating stack (32, 142). Theanisotropic etch can be, for example, a series of reactive ion etches.The top surface of the substrate 10 may be used as an etch stop layerfor the anisotropic etch. The sidewalls of line trenches 149 can besubstantially vertical, or can be tapered. The patterned lithographicmaterial stack can be subsequently removed, for example, by ashing.

In one embodiment, an overetch into the semiconductor material of thesubstrate 10 may be optionally performed after the top surface of thesubstrate 10 is physically exposed at a bottom of each line trench. Theoveretch may be performed prior to, or after, removal of thelithographic material stack. If the overetch is performed, the recessedsurfaces of the semiconductor material layer may be vertically offsetfrom the undressed top surfaces of the semiconductor material layer by arecess depth. The recess depth can be, for example, in a range from 0 nmto 50 nm, although lesser and greater recess depths can also beemployed. The overetch is optional, and may be omitted. If the overetchis not performed, the bottom surface of each line trench 149 can becoplanar with the topmost surface of the semiconductor material layer.Each of the line trenches 149 can include a pair of parallel sidewallsthat extends substantially perpendicular to the topmost surface of thesubstrate 10. The region in which the array of line trenches 149 isformed is herein referred to as a device region. Each line trench 149vertically extends through the alternating stack (32, 142) and laterallyextends along a first horizontal direction, which is the lengthwisedirection of the line trench 149.

Referring to FIGS. 4A and 4B, a series of contiguous material layersincluding at least one blocking dielectric layer 502L, a memory materiallayer 504L, a tunneling dielectric layer 505L, and a semiconductormaterial layer 160L can be sequentially deposited in the line trenches149 as a memory film layer 50L. The at least one blocking dielectriclayer 502L can include, for example, a first blocking dielectric layer501L and a second blocking dielectric layer 503L.

The first blocking dielectric layer 501L can be deposited on thesidewalls of each line trench 149 by a conformal deposition method. Thefirst blocking dielectric layer 501L includes a dielectric material,which can be a dielectric metal oxide. As used herein, a dielectricmetal oxide refers to a dielectric material that includes at least onemetallic element and at least oxygen. The dielectric metal oxide mayconsist essentially of the at least one metallic element and oxygen, ormay consist essentially of the at least one metallic element, oxygen,and at least one non-metallic element such as nitrogen. In oneembodiment, the first blocking dielectric layer 501L can include adielectric metal oxide having a dielectric constant greater than 7.9,i.e., having a dielectric constant greater than the dielectric constantof silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide(Al₂O₃), hafnium oxide (HfO₂), lanthanum oxide (LaO₂), yttrium oxide(Y₂O₃), tantalum oxide (Ta₂O₅), silicates thereof, nitrogen-dopedcompounds thereof, alloys thereof, and stacks thereof. The firstblocking dielectric layer 501L can be deposited, for example, bychemical vapor deposition (CVD), atomic layer deposition (ALD), pulsedlaser deposition (PLD), liquid source misted chemical deposition, or acombination thereof. The thickness of the first blocking dielectriclayer 501L can be in a range from 1 nm to 20 nm, although lesser andgreater thicknesses can also be employed. The first blocking dielectriclayer 501L can subsequently function as a dielectric material portionthat blocks leakage of stored electrical charges to control gateelectrodes. In one embodiment, the first blocking dielectric layer 501Lincludes aluminum oxide.

The second blocking dielectric layer 503L can be formed on the firstblocking dielectric layer 501L. The second blocking dielectric layer503L can include a dielectric material that is different from thedielectric material of the first blocking dielectric layer 501L. In oneembodiment, the second blocking dielectric layer 503L can includesilicon oxide, a dielectric metal oxide having a different compositionthan the first blocking dielectric layer 501L, silicon oxynitride,silicon nitride, or a combination thereof. In one embodiment, the secondblocking dielectric layer 503L can include silicon oxide. The secondblocking dielectric layer 503L can be formed by a conformal depositionmethod such as low pressure chemical vapor deposition, atomic layerdeposition, or a combination thereof. The thickness of the secondblocking dielectric layer 503L can be in a range from 1 nm to 20 nm,although lesser and greater thicknesses can also be employed.

Subsequently, the memory material layer 504L, the tunneling dielectriclayer 505L, and the semiconductor material layer 160L can besequentially formed. In one embodiment, the memory material layer 504Lcan be a charge trapping material including a dielectric charge trappingmaterial, which can be, for example, silicon nitride. Alternatively, thememory material layer 504L can include a conductive material such asdoped polysilicon or a metallic material that is patterned into multipleelectrically isolated portions, for example, by being formed withinlateral recesses into second material layers 142. In one embodiment, thememory material layer 504L includes a silicon nitride layer.

The memory material layer 504L can be formed as a single memory materiallayer of homogeneous composition, or can include a stack of multiplememory material layers. The multiple memory material layers, ifemployed, can comprise a plurality of spaced-apart floating gatematerial layers that contain conductive materials (e.g., metal such astungsten, molybdenum, tantalum, titanium, platinum, ruthenium, andalloys thereof, or a metal silicide such as tungsten silicide,molybdenum silicide, tantalum silicide, titanium silicide, nickelsilicide, cobalt silicide, or a combination thereof) and/orsemiconductor materials (e.g., polycrystalline or amorphoussemiconductor material including at least one elemental semiconductorelement or at least one compound semiconductor material). Alternativelyor additionally, the memory material layer 504L may comprise aninsulating charge trapping material, such as one or more silicon nitridesegments. Alternatively, the memory material layer 504L may compriseconductive nanoparticles such as metal nanoparticles, which can be, forexample, ruthenium nanoparticles. The memory material layer 504L can beformed, for example, by chemical vapor deposition (CVD), atomic layerdeposition (ALD), physical vapor deposition (PVD), or any suitabledeposition technique for storing electrical charges therein. Thethickness of the memory material layer 504L can be in a range from 2 nmto 20 nm, although lesser and greater thicknesses can also be employed.

The tunneling dielectric layer 505L includes a dielectric materialthrough which charge tunneling can be performed under suitableelectrical bias conditions. The charge tunneling may be performedthrough hot-carrier injection or by Fowler-Nordheim tunneling inducedcharge transfer depending on the mode of operation of the monolithicthree-dimensional NAND string memory device to be formed. The tunnelingdielectric layer 505L can include silicon oxide, silicon nitride,silicon oxynitride, dielectric metal oxides (such as aluminum oxide andhafnium oxide), dielectric metal oxynitride, dielectric metal silicates,alloys thereof, and/or combinations thereof. In one embodiment, thetunneling dielectric layer 505L can include a stack of a first siliconoxide layer, a silicon oxynitride layer, and a second silicon oxidelayer, which is commonly known as an ONO stack. In one embodiment, thetunneling dielectric layer 505L can be a stack including, from outsideto inside, an outer silicon oxide layer 506L, a silicon nitride layer507L, and an inner silicon oxide layer 508L. In one embodiment, thetunneling dielectric layer 505L can include a silicon oxide layer thatis substantially free of carbon or a silicon oxynitride layer that issubstantially free of carbon. The thickness of the tunneling dielectriclayer 505L can be in a range from 2 nm to 20 nm, although lesser andgreater thicknesses can also be employed.

The semiconductor material layer 160L includes a semiconductor materialsuch as at least one elemental semiconductor material, at least oneIII-V compound semiconductor material, at least one II-VI compoundsemiconductor material, at least one organic semiconductor material, orother semiconductor materials known in the art. In one embodiment, thesemiconductor material layer 160L includes amorphous silicon orpolysilicon. The semiconductor material layer 160L can be formed by aconformal deposition method such as low pressure chemical vapordeposition (LPCVD). The thickness of the semiconductor material layer160L can be in a range from 2 nm to 10 nm, although lesser and greaterthicknesses can also be employed. A line cavity 149′ is formed in thevolume of each memory opening 49 that is not filled with the depositedmaterial layers (501L, 503L, 504L, 505L, 601L).

Referring to FIGS. 5A and 5B, a dielectric material can be deposited inthe line trenches 149 to fill the line cavities 149′. The dielectricmaterial is concurrently deposited over the topmost surface of thesemiconductor material layer 160L. The deposited dielectric materialforms a contiguous dielectric material structure that fills the linecavities 149′ and overlies the top surface of the semiconductor materiallayer 160L. The contiguous dielectric material structure is hereinreferred to as a first dielectric cap material layer 62L. The firstdielectric cap material layer 62L includes a dielectric material such assilicon oxide, organosilicate glass (OSG), silicon nitride, a dielectricmetal oxide, or a combination thereof. The thickness of the firstdielectric cap material layer 62L, as measured above the topmost surfaceof the semiconductor material layer 160L, can be greater than one halfof the width of the line cavities 149′. For example, the thickness ofthe first dielectric cap material layer 62L can be in a range from 10 nmto 100 nm, although lesser and greater thicknesses can also be employed.

Referring to FIGS. 6A and 6B, a photoresist layer 57 is applied over thefirst dielectric cap material layer 62L, and is lithographicallypatterned to mask areas in the shapes of strips that straddle the linetrenches. In one embodiment, the lengthwise direction of the patternedstrips of the photoresist layer 57 can be perpendicular to thelengthwise direction of the line trenches. In one embodiment, the widthof each patterned strip of the photoresist layer 57 can be uniform, andcan be the same across a plurality of patterned strips of thephotoresist layer 57. In one embodiment, the width of the patternedstrips of the photoresist layer 57 can be selected from a range from 10nm to 100 nm, although lesser and greater widths can also be employed.In one embodiment, lithographic methods such as photoresist trimming orpitch multiplication techniques can be employed to provide a pluralityof patterned strips of photoresist layer 57 that extend along thewidthwise direction of the line trenches. In one embodiment, thelengthwise direction of the patterned strips of the photoresist layer 57can be perpendicular to the lengthwise direction of the line trenches.

The pattern in the photoresist layer 57 can be transferred through thefirst dielectric cap material layer 62L by an anisotropic etch thatetches the dielectric material of the first dielectric cap materiallayer 62L and the semiconductor material of the semiconductor materiallayer 160L. In one embodiment, the anisotropic etch can comprise a firstetch step in which the dielectric material of the first dielectric capmaterial layer 62L is etched selective to the semiconductor material ofthe semiconductor material layer 160L, and a second step in which thesemiconductor material of the semiconductor material layer 160L isetched.

Each remaining portion of the first dielectric cap material layer 62Lconstitutes a dielectric cap material portion 62. Each dielectric capmaterial portion 62 includes a horizontal strip laterally extendingalong the first horizontal direction, and at least one first verticallyextending dielectric pillar portion that protrudes downward into theline trenches. In one embodiment, each first vertically extendingdielectric portion may have a shape of a rectangular column, i.e., acolumn having a rectangular horizontal cross-sectional area. Eachremaining portion of the semiconductor material layer 160L constitutes asemiconductor strip structure 160, which can have a uniform width, andincludes at least two upper horizontal portions located over the topmosthorizontal surface of the memory film layer 50L, at least one pair ofvertical portions located within the line trench, and at least one lowerhorizontal portion located in proximity to a bottom surface of the linetrench.

A plurality of semiconductor strip structures 160 can be formed, whichstraddles each of the at least one line trench (that extends along afirst horizontal direction). The plurality of semiconductor stripstructures 160 extends along a second horizontal direction that isdifferent from the first horizontal direction. In one embodiment, thesecond horizontal direction can be perpendicular to the first horizontaldirection. The strips of semiconductor strip structures 160 arelaterally spaced apart from one another. A discrete trench 59 can beformed in each volume within a line trench from which the materials ofthe semiconductor material layer 160L and the first dielectric capmaterial layer 62L are etched. The discrete trenches 59 can form atwo-dimensional array of trenches with a first periodicity (pitch) thatis the same as the periodicity of the line trenches along the firsthorizontal direction and with a second periodicity that is the same asthe periodicity of the strips of the semiconductor strip structures 160along the second horizontal direction. Each semiconductor stripstructure 160 can include a plurality of semiconductor channels forthree-dimensional memory devices.

In one embodiment, at least a portion of the memory film layer 50L canbe patterned collaterally during the second step of the anisotropicetch, or by an additional processing step of the anisotropic etch. Asused herein, a tunneling dielectric 505 refers to a remaining contiguousportion of the tunneling dielectric layer 505L after the anisotropicetch, which may be patterned into discrete strips after the anisotropicetch or may be present as a single contiguous layer underlying thesemiconductor strip structures 160. A charge trapping layer 504 refersto each remaining contiguous portion of the memory film layer 504L,which may be patterned into discrete strips after the anisotropic etchor may be present as a single contiguous layer. A blocking dielectric502 refers to each remaining contiguous portion of the blockingdielectric layer 502L. In one embodiment, a tunneling dielectric 505 caninclude an ONO stack. In this case, the tunneling dielectric 505 caninclude a stack including an outer silicon oxide portion 506, a siliconnitride portion 507, and an inner silicon oxide portion 508. In oneembodiment, each blocking dielectric 502 can include a first blockingdielectric 501 that is a portion of the first blocking dielectric layer501L and a second blocking dielectric 503 that is a portion of thesecond blocking dielectric layer 503L.

In one embodiment, at least one layer among the plurality of contiguousmaterial layers of the memory film layer 50L can be patterned with thesame pattern as the plurality of semiconductor strip structures 160 bythe anisotropic etch. The anisotropic etch can employ another layeramong the plurality of contiguous material layers in the memory filmlayer 50L as an etch stop layer. In an illustrative example, thetunneling dielectric layer 505L can be patterned into tunnelingdielectrics 505 in a strip pattern employing the memory film layer 504Las an etch stop layer. In another example, the memory film layer 504Lcan be patterned into charge trapping layers 504 employing the blockingdielectric layer 502L as an etch stop layer.

The anisotropic etch can form a memory film 50 on a bottom surface ofeach line trench. Each memory film 50 can include a tunneling dielectric505, a charge trapping layer 504, and a blocking dielectric 502. Theplurality of semiconductor strip structures 160 is formed over ahorizontal portion of the memory film 50, and is electrically isolatedfrom the substrate 10 by the horizontal portion of the memory film 50.The photoresist layer 57 can be removed, for example, by ashing.

Referring to FIGS. 7A and 7B, a second dielectric cap material layer 64can be deposited into the array of discrete cavities 59 and over the topsurface of the dielectric cap material portions 62. The discretecavities 59 are filled with the dielectric material of the seconddielectric cap material layer 64. The second dielectric cap materiallayer 64 includes a dielectric material such as silicon oxide,organosilicate glass (OSG), silicon nitride, a dielectric metal oxide,or a combination thereof. The second dielectric cap material layer 64can have the same material as, or a material different from, the atleast one dielectric cap material portion 62. The second dielectric capmaterial layer 64 can be planarized, for example, by chemical mechanicalplanarization (CMP), a recess etch, or a combination thereof.

In one embodiment, the second dielectric cap material layer 64 includesa planar portion having a planar top surface and located above ahorizontal plane including top surfaces of the dielectric cap materialportions 62, strip portions extending along the first horizontaldirection and located between horizontal portions of the dielectric capmaterial portions 62 and the semiconductor strip structures 160, belowthe horizontal plane including top surfaces of the dielectric capmaterial portions, and above the topmost surface of the alternatingstack (32, 142), and second vertically extending dielectric pillarportions that are located between first vertically extending dielectricpillar portions of the dielectric cap material portions 62. Within eachline trench, an alternating plurality of first vertically extendingdielectric pillar portions of the dielectric cap material portions 62and second vertically extending dielectric pillar portions of the seconddielectric cap material layer 64 is provided, which extends along thefirst horizontal direction.

Referring to FIGS. 8A and 8B, a photoresist layer (not shown) can beapplied over the second dielectric cap material layer 64, and can belithographically patterned to form openings that overlie the areas ofthe alternating pluralities of vertically extending dielectric pillarportions of the second dielectric cap material layer 64 and verticallyextending dielectric pillar portions of the dielectric cap materialportions 62. Each opening in the photoresist layer can laterally extendalong the first horizontal direction, which is the lengthwise directionof the line trenches. Each opening in the photoresist layer can straddlebottommost horizontal portions of the plurality of semiconductor stripstructures 160 that are located in proximity to bottom surfaces of theline trenches. In one embodiment, the lengthwise edges of an opening inthe photoresist layer can be parallel to inner sidewalls of portions ofa plurality of semiconductor strip structures 160 that are locatedwithin a same line trench. In one embodiment, lengthwise edges of anopening in the photoresist layer can laterally offset outward along thesecond horizontal direction from inner sidewalls of portions of aplurality of semiconductor strip structures 160 that are located withina same line trench.

The portions of the second dielectric cap material layer 64 and theportions of the dielectric cap material portions 62 within the area ofeach opening in the photoresist layer is removed employing ananisotropic etch that is selective to the semiconductor material of theplurality of semiconductor strip structures 160. The anisotropic etchcan form a plurality of line cavities 69 that extend along the firsthorizontal direction. Each line cavity 69 can straddle a plurality ofsemiconductor strip structures 160. For each semiconductor channel thata line cavity 69 straddles, a pair of substantially vertical sidewallsof the semiconductor strip structure 160 and a horizontal top surface ofa bottom portion of the semiconductor strip structure 160 can bephysically exposed within the line cavity 69. Thus, sidewalls of aplurality of semiconductor strip structures 160 and top surfaces ofhorizontal bottom portions of the plurality of semiconductor channel canbe physically exposed within the line cavity 69.

Referring to FIGS. 9A and 9B, a back gate dielectric 166 can bedeposited within the line cavities 69. In one embodiment, the back gatedielectric 166 can be deposited as a single contiguous layer by aconformal deposition method such as low pressure chemical vapordeposition (LPCVD) and/or atomic layer deposition (ALD). The back gatedielectric 166 can include silicon oxide, silicon oxynitride, adielectric metal oxide, or a stack thereof. The thickness of the backgate dielectric 166 can be in a range from 1 nm to 10 nm, althoughlesser and greater thicknesses can also be employed. The back gatedielectric 166 can be formed on inner sidewalls of the plurality ofsemiconductor strip structures 160.

A back gate electrode 168 can be formed within each remaining portion ofthe line cavities 69 by deposition of at least one conductive materialand removal of the at least one conductive material from above thetopmost surface of the back gate dielectric 166. Each remaining portionof the at least one conductive material constitutes a back gateelectrode 168. In one embodiment, the at least one conductive materialcan include a metallic liner material such as TiN, TaN, and/or WN, and ametallic fill material such as W, Al, Cu, or a combination thereof.

Each back gate electrode 168 can be formed on inner sidewalls of theback gate dielectric 166. Each back gate dielectric 166 extends alongthe first horizontal direction within a line trench, and contactssurfaces of at least two of the plurality of semiconductor stripstructures 160. Each back gate electrode 168 straddles the at least twoof the plurality of semiconductor channels.

If the second material layers 142 are sacrificial material layers, thesacrificial material of the second material layers 142 can be replacedwith a conductive material, which can include, for example, a conductivemetallic nitride material (such as TiN, TaN, and WN), an elemental metalor an alloy thereof (such as W, Al, Cu, and alloys thereof), and a dopedsemiconductor material. Replacement of the sacrificial material with aconductive material can be performed, for example, by forming at leastone trench that is intersects the alternating stack (32, 142), removingthe sacrificial material of the second material layers 142 selective tothe first material layers 32 and various structures located in the linetrenches, and by depositing a conductive material in the backsiderecesses formed by removal of the sacrificial material. Alternatively,if the second material layer 142 are conductive material layers (forexample, doped semiconductor layers or metallic material layers),replacement of the second material layers 142 with a conductive materialcan be omitted.

Contact via structures (not shown) can be formed through a topmosthorizontal portion of the back gate dielectric 166 (if not removedduring planarization of the conductive material of the back gateelectrodes 168), and through the second dielectric cap material layer 64and the dielectric cap material portions 62 to horizontal top portionsof the semiconductor strip structures 160 that are located above ahorizontal plane including the topmost surface of the alternating stack(32, 142). Each semiconductor channel corresponds to a portion of asemiconductor strip structure 160 that extends between a first contactvia structure located on one side of a line trench and a second contactvia structure located on the other side of the line trench. Eachsemiconductor channel includes a U-shaped portion of a semiconductorstrip structure 160, a first horizontal portion adjoined to one end ofthe U-shaped portion and contacting a contact via structure (which canfunction as a source contact via structure), and a second horizontalportion adjoined to another end of the U-shaped portion and contactinganother contact via structure (which can function as a drain contact viastructure). In one embodiment, the horizontal portions of eachsemiconductor strip structure can be doped to form active regions thatfunction as source regions and/or drain regions.

A U-shaped portion of a semiconductor strip structure 160 is locatedwithin a line trench and includes a horizontal semiconductor channelportion adjacent to a bottom of the line trench and a pair of verticallyextending semiconductor channel portions adjoined to the horizontalsemiconductor channel portion. A first horizontal portion of thesemiconductor strip structure 160 is adjoined to a top end of a firstvertically extending semiconductor channel portion among the pair ofvertically extending semiconductor channel portions. A second horizontalportion of the semiconductor strip structure 160 is adjoined to a topend of a second vertically extending semiconductor channel portion amongthe pair of vertically extending semiconductor channel portions. Thecontact via structure that contacts the first horizontal portion of thesemiconductor strip structure 160 can function as a source-side contactvia structure, and the contact via structure that contacts the secondhorizontal portion of the semiconductor strip structure 160 can functionas a drain-side contact via structure.

A memory film 50 can be located on the first sidewall, the secondsidewall, and the top surface of the substrate 10. The memory film 50can comprise a tunneling dielectric 505 in contact with at least one ofthe plurality of semiconductor strip structures 160. In one embodiment,the memory film 50 can comprise an element selected from a chargetrapping layer and floating gate material portions. The back gatedielectric 166 can straddle at least two of the plurality ofsemiconductor strip structures 160, and the back gate electrode 168 canstraddle at least two of the plurality of semiconductor strip structures160. In one embodiment, the back gate dielectric 166 does not include acharge storage material or a charge trapping material (such as siliconnitride).

Each of the plurality of semiconductor strip structures 160 can includea respective first horizontal portion located over the stack (32, 142)and a respective second horizontal portion (32, 142) located at a bottomportion of the line trench. Each of the plurality of semiconductor stripstructures 160 can further comprise a respective first vertical portionadjoined to the respective first horizontal portion and the respectivesecond horizontal portion and contacting a portion of the first sidewallof the line trench, and a respective second vertical portion adjoined toa respective third horizontal portion located over the stack and therespective second horizontal portion and contacting a portion of thesecond sidewall of the line trench. The line trench can laterally extendalong a first horizontal direction, and each of the plurality ofsemiconductor strip structures 160 can laterally extend along a secondhorizontal direction that is different from the first horizontaldirection. In one embodiment, each of the plurality of semiconductorstrip structures 160 can have a respective uniform width that isinvariant under translation along the second horizontal direction.

Referring to FIGS. 10A and 10B, a second exemplary structure accordingto a second embodiment of the present disclosure can be derived from thefirst exemplary structure illustrated in FIGS. 1A and 1B by forming asource line layer 12 in an upper portion of the substrate 10. In oneembodiment, the source line layer 12 can be formed by implantingelectrical dopants into an upper portion of a substrate semiconductorlayer 9 of the substrate 10. Alternatively or additionally, the sourceline layer 12 can be formed by depositing a doped semiconductor materiallayer, for example, by a selective epitaxy process. The source linelayer 12 can be formed as a plurality of disjoined portions that arelaterally spaced from one another along one direction, which can be afirst horizontal direction along which line trenches to be subsequentlyformed extend. In an illustrative example, if a vertical NAND deviceemploying an n-doped drain region and an n-doped source region is to beformed, the source line layer 12 can be a p-doped semiconductor layer.The thickness of the source line layer 12 can be in a range from 10 nmto 300 nm, although lesser and greater thicknesses can also be employed.An alternating stack (32, 142) of first material layers 32 and secondmaterial layers 142 can be formed above the source line layer 12 in thesame manner as in the first embodiment.

Referring to FIGS. 11A and 11B, the processing steps of FIGS. 2A and 2Bcan be performed as in the first embodiment.

Referring to FIGS. 12A and 12B, the processing steps of FIGS. 3A and 3Bcan be performed as in the first embodiment. A top surface of the sourceline layer 12 can be physically exposed at the bottom of each linetrench 149.

Referring to FIGS. 13A and 13B, the processing steps of FIGS. 4A and 4Bcan be performed to form the memory film layer 50L as in the firstembodiment. A first semiconductor material layer 601L can be depositedon the memory film layer 50L. The first semiconductor material layer601L includes a semiconductor material such as at least one elementalsemiconductor material, at least one III-V compound semiconductormaterial, at least one II-VI compound semiconductor material, at leastone organic semiconductor material, or other semiconductor materialsknown in the art. In one embodiment, the first semiconductor materiallayer 601L includes amorphous silicon or polysilicon. The firstsemiconductor material layer 601L can be formed by a conformaldeposition method such as low pressure chemical vapor deposition(LPCVD). The thickness of the first semiconductor material layer 601Lcan be in a range from 2 nm to 10 nm, although lesser and greaterthicknesses can also be employed. A line cavity 149′ is formed in thevolume of each line trench that is not filled with the depositedmaterial layers (501L, 503L, 504L, 5051, 601L).

Referring to FIGS. 14A and 14B, a photoresist layer (not shown) can beapplied over the second exemplary structure, and can be lithographicallypatterned to form openings in the areas of the line cavities 149′. Inone embodiment, peripheries of an opening in the patterned photoresistlayer can cover the sidewalls of the first semiconductor material layer601L inside a line trench. In another embodiment, peripheries of anopening in the patterned photoresist layer can overlie a topmost surfaceof the first semiconductor material layer 601L. In one embodiment, theshape of each opening in the patterned photoresist layer can besubstantially the same as the shape of the horizontal surface of abottom portion of the first semiconductor material layer 601L within anunderlying line trench. Alternatively, a patterning process that doesnot employ a photoresist layer can be employed. In this case, ananisotropic etch process can be performed to remove horizontal portionsof the first semiconductor material layer 601L and the memory film layer50L, and to form an opening at a bottom of each line trench so that atop surface of the source line layer 12 is physically exposed at abottom portion of each line trench. The vertical portions of the firstsemiconductor material layer 601L and the memory film layer 50L canremain on sidewalls of the line trenches.

An anisotropic etch can be performed to form openings through the bottomportions of the first semiconductor material layer 601L located withinthe line trenches. The horizontal portions of the first semiconductormaterial layer 601L, the tunneling dielectric layer 505L, the memorymaterial layer 504L, and optionally one or more of the at least oneblocking dielectric layer 502L at a bottom of each line cavity 149′ canbe removed to form openings in remaining portions thereof. Each of thefirst semiconductor material layer 601L, the tunneling dielectric layer505L, the memory material layer 504L, and the at least one blockingdielectric layer 502L can be etched by anisotropic etch process.

A second semiconductor material layer 602L can be deposited directly onthe semiconductor surface of the source line layer 12, and directly onthe first semiconductor material layer 601L. The second semiconductormaterial layer 602L includes a semiconductor material such as at leastone elemental semiconductor material, at least one III-V compoundsemiconductor material, at least one II-VI compound semiconductormaterial, at least one organic semiconductor material, or othersemiconductor materials known in the art. In one embodiment, the secondsemiconductor material layer 602L includes amorphous silicon orpolysilicon. The second semiconductor material layer 602L can be formedby a conformal deposition method such as low pressure chemical vapordeposition (LPCVD). The thickness of the second semiconductor materiallayer 602L can be in a range from 2 nm to 10 nm, although lesser andgreater thicknesses can also be employed. The second semiconductormaterial layer 602L may partially fill the line cavity 149′ in each linetrench. The first and second semiconductor material layers (601L, 602L)collectively constitute a semiconductor material layer 160L.

A dielectric material can be deposited in the line trenches 149 to fillthe line cavities 149′. The dielectric material is concurrentlydeposited over the topmost surface of the semiconductor material layer160L. The deposited dielectric material forms a contiguous dielectricmaterial structure that fills the line cavities 149′ and overlies thetop surface of the semiconductor material layer 160L. The contiguousdielectric material structure is herein referred to as a firstdielectric cap material layer 62L. The first dielectric cap materiallayer 62L includes a dielectric material such as silicon oxide,organosilicate glass (OSG), silicon nitride, a dielectric metal oxide,or a combination thereof. The thickness of the first dielectric capmaterial layer 62L, as measured above the topmost surface of thesemiconductor material layer 160L, can be greater than one half of thewidth of the line cavities 149′. For example, the thickness of the firstdielectric cap material layer 62L can be in a range from 10 nm to 100nm, although lesser and greater thicknesses can also be employed.

Referring to FIGS. 15A and 15B, the processing steps of FIGS. 6A and 6Bcan be performed to pattern the first dielectric cap material layer 62Linto dielectric cap material portions 62, and to pattern thesemiconductor material layer 160L into a plurality of semiconductorstrip structures 160 in the same manner as in the first embodiment. Forexample, a photoresist layer 57 can be applied over the first dielectriccap material layer 62L, and is lithographically patterned to mask areasin the shapes of strips that straddle the line trenches. In oneembodiment, the lengthwise direction of the patterned strips of thephotoresist layer 57 can be perpendicular to the lengthwise direction ofthe line trenches.

The pattern in the photoresist layer 57 can be transferred through thefirst dielectric cap material layer 62L by an anisotropic etch thatetches the dielectric material of the first dielectric cap materiallayer 62L and the semiconductor material of the semiconductor materiallayer 160L. In one embodiment, the anisotropic etch can comprise a firstetch step in which the dielectric material of the first dielectric capmaterial layer 62L is etched selective to the semiconductor material ofthe semiconductor material layer 160L, and a second step in which thesemiconductor material of the semiconductor material layer 160L isetched.

Each remaining portion of the first dielectric cap material layer 62Lconstitutes a dielectric cap material portion 62. Each dielectric capmaterial portion 62 includes a horizontal strip laterally extendingalong the first horizontal direction, and at least one first verticallyextending dielectric pillar portion that protrudes downward into theline trenches. In one embodiment, each first vertically extendingdielectric portion may have a shape of a rectangular column, i.e., acolumn having a rectangular horizontal cross-sectional area. Eachremaining portion of the semiconductor material layer 160L constitutes asemiconductor strip structure 160, which can have a uniform width, andincludes at least two upper horizontal portions located over the topmosthorizontal surface of the memory film layer 50L, at least one pair ofvertical portions located within the line trench, and at least one lowerhorizontal portion located in proximity to a bottom surface of the linetrench.

A plurality of semiconductor strip structures 160 can be formed, whichstraddles each of the at least one line trench (that extends along afirst horizontal direction). The plurality of semiconductor stripstructures 160 extends along a second horizontal direction that isdifferent from the first horizontal direction. In one embodiment, thesecond horizontal direction can be perpendicular to the first horizontaldirection. The strips of semiconductor strip structures 160 arelaterally spaced apart from one another. A discrete trench 59 can beformed in each volume within a line trench from which the materials ofthe semiconductor material layer 160L and the first dielectric capmaterial layer 62L are etched. The discrete trenches 59 can form atwo-dimensional array of trenches with a first periodicity (pitch) thatis the same as the periodicity of the line trenches along the firsthorizontal direction and with a second periodicity that is the same asthe periodicity of the strips of the semiconductor strip structures 160along the second horizontal direction.

In one embodiment, at least a portion of the memory film layer 50L canbe patterned collaterally during the second step of the anisotropicetch, or by an additional processing step of the anisotropic etch. Asused herein, a tunneling dielectric 505 refers to a remaining contiguousportion of the tunneling dielectric layer 505L after the anisotropicetch, which may be patterned into discrete strips after the anisotropicetch or may be present as a single contiguous layer underlying thesemiconductor strip structures 160. A charge trapping layer 504 refersto each remaining contiguous portion of the memory film layer 504L,which may be patterned into discrete strips after the anisotropic etchor may be present as a single contiguous layer. A blocking dielectric502 refers to each remaining contiguous portion of the blockingdielectric layer 502L. In one embodiment, a tunneling dielectric 505 caninclude an ONO stack. In this case, the tunneling dielectric 505 caninclude a stack including an outer silicon oxide portion 506, a siliconnitride portion 507, and an inner silicon oxide portion 508. In oneembodiment, each blocking dielectric 502 can include a first blockingdielectric 501 that is a portion of the first blocking dielectric layer501L and a second blocking dielectric 503 that is a portion of thesecond blocking dielectric layer 503L.

In one embodiment, at least one layer among the plurality of contiguousmaterial layers of the memory film layer 50L can be patterned with thesame pattern as the plurality of semiconductor strip structures 160 bythe anisotropic etch. The anisotropic etch can employ another layeramong the plurality of contiguous material layers in the memory filmlayer 50L as an etch stop layer. In an illustrative example, thetunneling dielectric layer 505L can be patterned into tunnelingdielectrics 505 in a strip pattern employing the memory film layer 504Las an etch stop layer. In another example, the memory film layer 504Lcan be patterned into charge trapping layers 504 employing the blockingdielectric layer 502L as an etch stop layer.

The anisotropic etch can form a memory film 50 on a bottom surface ofeach line trench. Each memory film 50 can include a tunneling dielectric505, a charge trapping layer 504, and a blocking dielectric 502. Theplurality of semiconductor strip structures 160 is formed over ahorizontal portion of the memory film 50, and is electrically isolatedfrom the substrate 10 by the horizontal portion of the memory film 50.The photoresist layer 57 can be removed, for example, by ashing.

Referring to FIGS. 16A and 16B, the processing steps of FIGS. 7A and 7Bcan be performed to form a second dielectric cap material layer 64 inthe same manner as in the first embodiment.

Referring to FIGS. 17A and 17B, the processing steps of FIGS. 8A and 8Bcan be performed to form line trenches 69 in the same manner as in thefirst embodiment.

Referring to FIGS. 18A and 18B, the processing steps of FIGS. 9A and 9Bcan be performed to form a back gate dielectric 166 and back gateelectrodes 168 in the same manner as in the first embodiment.

If the second material layers 142 are sacrificial material layers, thesacrificial material of the second material layers 142 can be replacedwith a conductive material, which can include, for example, a conductivemetallic nitride material (such as TiN, TaN, and WN), an elemental metalor an alloy thereof (such as W, Al, Cu, and alloys thereof), and a dopedsemiconductor material. Replacement of the sacrificial material with aconductive material can be performed, for example, by forming at leastone trench that is intersects the alternating stack (32, 142), removingthe sacrificial material of the second material layers 142 selective tothe first material layers 32 and various structures located in the linetrenches, and by depositing a conductive material in the backsiderecesses formed by removal of the sacrificial material. Alternatively,if the second material layer 142 are conductive material layers (forexample, doped semiconductor layers or metallic material layers),replacement of the second material layers 142 with a conductive materialcan be omitted.

A source region (not shown) can be formed in, or over, the substrate 10such that the source region contacts the source line layer 12. In oneembodiment, the source region can have a doping of an oppositeconductivity type than the doping of the source line layer 12. Abackside contact via structure (not shown) can be formed on each sourceregion through the stack of an alternating plurality of insulator layers32 and conductive material layers (which can be the second materiallayers 142 if the second material layers include a conductive material,or can be formed by replacement of the second material layers 142 if thesecond material layers include a sacrificial material). The backsidecontact via structure can be electrically isolated from the alternatingstack by a dielectric spacer.

Drain regions can be formed in horizontal portions of the semiconductorstrip structures 160 that overlie the alternating stack (32, 142), forexample, by implantation of electrical dopants, which can be p-typedopants or n-type dopants. Drain contact via structures (not shown) canbe formed through a topmost horizontal portion of the back gatedielectric 166 (if not removed during planarization of the conductivematerial of the back gate electrodes 168), and through the seconddielectric cap material layer 64 and the dielectric cap materialportions 62 to horizontal top portions of the semiconductor stripstructures 160 that are located above a horizontal plane including thetopmost surface of the alternating stack (32, 142).

During operation of the three-dimensional memory device, electricalcurrent can flow through a source-side contact via structure (not shown)extending through the alternating stack (32, 142), a source regionlocated in (or over) the substrate 10, the source line layer 12 locatedin (or over) a portion of the substrate 10, a vertically extendingportion of a semiconductor strip structure 160, a drain region formed ina horizontal portion of the semiconductor strip structure 160, and adrain-side contact via structure that extends through the alternatingstack (32, 142). A vertical portion of the semiconductor strip structure160 functions as a portion of a semiconductor channel for athree-dimensional memory device. A horizontal portion of thesemiconductor strip structure 160 adjoined to the vertical portion ofthe semiconductor strip structure 160 can be a drain region. The contactvia structure that contacts the horizontal portion of the semiconductorstrip structure 160 can function as a drain-side contact via structure.

A memory film 50 can be located on the first sidewall, the secondsidewall, and the top surface of the substrate 10. The memory film 50can comprise a tunneling dielectric 505 in contact with at least one ofthe plurality of semiconductor strip structures 160. In one embodiment,the memory film 50 can comprise an element selected from a chargetrapping layer and floating gate material portions. The back gatedielectric 166 can straddle at least two of the plurality ofsemiconductor strip structures 160, and the back gate electrode 168straddle at least two of the plurality of semiconductor strip structures160. The semiconductor channels in the semiconductor strip structure 160can be electrically shorted to the source line layer 12 located in (orover) the substrate 10. Each source line layer 12 can be laterallyspaced from, and electrically isolated from, adjacent semiconductorchannel layers 12 along the first horizontal direction (which is thedirection along which the line trenches extend). The source line layers12 can extend along the second horizontal direction that isperpendicular to the first horizontal direction.

Each of the plurality of semiconductor strip structures 160 can includea respective first horizontal portion located over the stack (32, 142)and a respective second horizontal portion (32, 142) located at a bottomportion of the line trench. Each of the plurality of semiconductor stripstructures 160 can further comprise a respective first vertical portionadjoined to the respective first horizontal portion and the respectivesecond horizontal portion and contacting a portion of the first sidewallof the line trench, and a respective second vertical portion adjoined toa respective third horizontal portion located over the stack and therespective second horizontal portion and contacting a portion of thesecond sidewall of the line trench. The line trench can laterally extendalong a first horizontal direction, and each of the plurality ofsemiconductor strip structures 160 can laterally extend along a secondhorizontal direction that is different from the first horizontaldirection. In one embodiment, each of the plurality of semiconductorstrip structures 160 can have a respective uniform width that isinvariant under translation along the second horizontal direction.

Referring to FIG. 19, a third exemplary structure according to a thirdembodiment of the present disclosure is shown. The third exemplarystructure includes a substrate 10, which includes a substratesemiconductor layer 9. The substrate semiconductor layer 9 is asemiconductor material layer located at least in an upper portion of asubstrate, and can include at least one elemental semiconductormaterial, at least one III-V compound semiconductor material, at leastone II-VI compound semiconductor material, at least one organicsemiconductor material, or other semiconductor materials known in theart. The substrate can have a major surface 7, which can be, forexample, a topmost surface of the substrate semiconductor layer 9. Themajor surface 7 can be a semiconductor surface. In one embodiment, themajor surface 7 can be a single crystalline semiconductor surface.

An optional dielectric material portion 13 can be formed within thesubstrate semiconductor layer 9, for example, by forming a shallowtrench in an upper portion of the substrate semiconductor layer 9,filling the shallow trench with a dielectric material, and removing anexcess portion of the dielectric material from above the top surface ofthe substrate semiconductor layer 9 employing a planarization processsuch as a chemical mechanical planarization (CMP) process. The remainingportion of the dielectric material constitutes the dielectric materialportion. The dielectric material portion includes a dielectric materialsuch as silicon oxide, silicon nitride, a dielectric metal oxide, or acombination thereof.

A patterned conductive material layer 14 can be formed on the topsurface of the dielectric material portion 13. The patterned conductivematerial layer 14 can be formed, for example, by depositing a layer of aconductive material over the substrate 10, and patterning the depositedconductive material by a combination of lithographic methods and an etchprocess. For example, a photoresist layer may be applied and patternedto mask a portion of the deposited conductive material, and unmaskedportions of the deposited conductive material can be removed by an etchprocess. The remaining portion of the conductive material constitutesthe patterned conductive material layer 14. In one embodiment, theconductive material layer 14 can be a metallic material layer. In oneembodiment, the conductive material layer 14 can include a stack, frombottom to top, of a conductive metallic nitride layer including aconductive metallic nitride (such as TiN, TaN, and WN) and a metallicmaterial layer including an elemental metal or an alloy thereof (such asW, Al, Cu, or an ally thereof). The thickness of the conductive materiallayer 14 can be in a range from 2 nm to 40 nm, although lesser andgreater thicknesses can also be employed. In one embodiment, the entireperiphery of the conductive material layer 14 can be entirely within anarea defined by the periphery of the dielectric material portion 13.

Alternatively, the conductive material layer 14 may be formed as a dopedsemiconductor layer within an upper portion of the substrate 10. In thiscase, the doped semiconductor layer can be electrically isolated fromthe substrate semiconductor layer 9 by a reverse-biased p-n junctionbetween the doped semiconductor layer and the substrate semiconductorlayer 9. The dielectric material portion 13 electrically isolated theconductive material layer 14 from the substrate semiconductor layer 9.

A bottommost insulator layer 132 can be formed over the substrate 10 andthe conductive material layer 14. The bottommost insulator layer 132includes an electrically insulating material. Electrically insulatingmaterials that can be employed for the bottommost insulator layer 132include, but are not limited to, silicon oxide (including doped orundoped silicate glass), silicon nitride, silicon oxynitride,organosilicate glass (OSG), spin-on dielectric materials, dielectricmetal oxides that are commonly known as high dielectric constant(high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.)and silicates thereof, dielectric metal oxynitrides and silicatesthereof, and organic insulating materials. In one embodiment, thebottommost insulator layer 132 can include the same material asinsulator layers to be subsequently formed. In one embodiment, thebottommost insulator layer 132 can include silicon oxide.

A temporary material layer 41 can be formed over the bottommostinsulator layer 132. The temporary material layer 41 includes a materialthat can be removed selective to a first material of the insulatorlayers to be subsequently formed and selective to a second material ofsacrificial material layers to be subsequently formed. As used herein, a“temporary material” refers to a material that is present on a structureduring at least one processing step, and is removed from the structureprior to completion of the structure, i.e., prior to the termination ofthe last processing step.

A stack of an alternating plurality of first material layers (which canbe insulating layers 32) and second material layers (which can besacrificial material layer 42) is formed over the top surface of thesubstrate, which can be, for example, on the top surface of thetemporary material layer 41. The alternating plurality of first materiallayers and second material layers may begin with an instance of thefirst material layers, and end with another instance of the firstmaterial layers. In one embodiment, an instance of the first elementsand an instance of the second elements may form a unit that is repeatedwith periodicity within the alternating plurality of layers.

Each first material layer includes a first material, and each secondmaterial layer includes a second material that is different from thefirst material. In one embodiment, each first material layer 32 can bean insulator layer, and each second material layer 142 can be asacrificial material layer. In this case, the stack can include analternating plurality of insulator layers 32 and sacrificial materiallayers 42.

The stack of the alternating plurality is herein referred to as analternating stack (32, 42). In one embodiment, the alternating stack(32, 42) can include insulator layers 32 composed of the first material,and sacrificial material layers 42 composed of a second materialdifferent from that of insulator layers 32. The first material of theinsulator layers 32 can be at least one electrically insulatingmaterial. As such, each insulator layer 32 can be an electricallyinsulating material layer. Electrically insulating materials that can beemployed for the insulator layers 32 include, but are not limited to,silicon oxide (including doped or undoped silicate glass), siliconnitride, silicon oxynitride, organosilicate glass (OSG), spin-ondielectric materials, dielectric metal oxides that are commonly known ashigh dielectric constant (high-k) dielectric oxides (e.g., aluminumoxide, hafnium oxide, etc.) and silicates thereof, dielectric metaloxynitrides and silicates thereof, and organic insulating materials. Inone embodiment, the first material of the insulator layers 32 can besilicon oxide.

The second material of the sacrificial material layers 42 is asacrificial material that can be removed selective to the first materialof the insulator layers 32. The sacrificial material layers 42 maycomprise an electrically insulating material, a semiconductor material,or a conductive material. The second material of the sacrificialmaterial layers 42 can be subsequently replaced with electricallyconductive electrodes which can function, for example, as control gateelectrodes of a vertical NAND device. Non-limiting examples of thesecond material include silicon nitride, an amorphous semiconductormaterial (such as amorphous silicon), and a polycrystallinesemiconductor material (such as polysilicon). In one embodiment, thesacrificial material layers 42 can be material layers that comprisesilicon nitride or a semiconductor material including germanium or asilicon-germanium alloy.

In one embodiment, the insulator layers 32 can include silicon oxide,and sacrificial material layers can include silicon nitride. The firstmaterial of the insulator layers 32 can be deposited, for example, bychemical vapor deposition (CVD). For example, if silicon oxide isemployed for the insulator layers 32, tetraethyl orthosilicate (TEOS)can be employed as the precursor material for the CVD process. Thesecond material of the sacrificial material layers 42 can be formed, forexample, CVD or atomic layer deposition (ALD).

The sacrificial material layers 42 can be suitably patterned so thatconductive material portions to be subsequently formed by replacement ofthe sacrificial material layers 42 can function as electricallyconductive electrodes, such as the control gate electrodes of themonolithic three-dimensional NAND string memory devices to besubsequently formed. The sacrificial material layers 42 may comprise aportion having a strip shape extending substantially parallel to themajor surface 7 of the substrate.

The thicknesses of the bottommost insulator layer 132, the temporarymaterial layer 41, the insulator layers 32, and the sacrificial materiallayers 42 can be in a range from 20 nm to 50 nm, although lesser andgreater thicknesses can be employed for each layer. The number ofrepetitions of the pairs of an insulator layer 32 and a sacrificialmaterial layer (e.g., a control gate electrode or a sacrificial materiallayer) 42 can be in a range from 2 to 1,024, and typically from 8 to256, although a greater number of repetitions can also be employed. Thetop and bottom gate electrodes in the stack may function as the selectgate electrodes. In one embodiment, each sacrificial material layer 42in the alternating stack (32, 42) can have a uniform thickness that issubstantially invariant within each respective sacrificial materiallayer 42.

In one embodiment, the bottommost insulator layer 132 and the insulatorlayers 32 can include silicon oxide, the sacrificial material layers 42can include silicon nitride, and the temporary material layer 41 caninclude a semiconductor material. The semiconductor material of thetemporary material layer 41 can be, for example, a Group IVsemiconductor material, a III-V compound semiconductor material, a II-VIsemiconductor material, an organic semiconductor material. In anillustrative example, the semiconductor material can be amorphoussilicon or polysilicon.

In another embodiment, the bottommost insulator layer 132 and theinsulator layers 32 can include silicon oxide, the sacrificial materiallayers 42 can include a semiconductor material that can be etchedselective to the semiconductor material of the semiconductor materiallayer 10, and the temporary material layer 41 can include siliconnitride. The semiconductor material of the sacrificial material layers42 can be, for example, germanium, a silicon-germanium alloy, a III-Vcompound semiconductor material, a II-VI semiconductor material, anorganic semiconductor material.

Referring to FIG. 20, a lithographic material stack (not shown)including at least a photoresist layer can be formed over thealternating stack (32, 42), and can be lithographically patterned toform openings therein. The pattern in the lithographic material stackcan be transferred through the entirety of the alternating stack (32,42) by at least one anisotropic etch that employs the patternedlithographic material stack as an etch mask. Portions of the alternatingstack (32, 42) underlying the openings in the patterned lithographicmaterial stack are etched to form memory openings 49. In other words,the transfer of the pattern in the patterned lithographic material stackthrough the alternating stack (32, 42) forms the memory openings 49 thatextend through the alternating stack (32, 42). The chemistry of theanisotropic etch process employed to etch through the materials of thealternating stack (32, 42) can alternate to optimize etching of thefirst and second materials in the alternating stack (32, 42). Theanisotropic etch can be, for example, a series of reactive ion etches.Optionally, the conductive material layer 14 may be used as an etch stoplayer between the alternating stack (32, 42) and the substrate. Thesidewalls of the memory openings 49 can be substantially vertical, orcan be tapered. The patterned lithographic material stack can besubsequently removed, for example, by ashing.

The memory openings 49 are formed through the alternating stack (32,42), the temporary material layer 41, and the bottommost insulator layer132 so that the memory openings 49 extend from the top surface of thealternating stack (32, 42) to the top surface of the conductive materiallayer 14 over the substrate 10. The region in which the array of memoryopenings 49 is formed is herein referred to as a device region. In oneembodiment, each memory openings 49 can have a cylindrical shape, and ahorizontal cross-sectional shape of each memory opening can be circular,elliptical, polygonal, or of a general curvilinear closed shape.

Referring to FIG. 21, a memory film layer and a semiconductor channellayer are sequentially deposited into the array of memory openings 49and over the alternating stack (32, 42). The memory film layer can havethe same material stack as the memory film layer 50L according to thefirst and second embodiments. The semiconductor channel layer can havethe same material composition and thickness as the semiconductormaterial layer 160L according to the first and second embodiments. Thesemiconductor channel layer is a semiconductor material layer, and caninclude an amorphous semiconductor material or a polycrystallinesemiconductor material.

The semiconductor channel layer and the memory film layer can beanisotropically etched to remove horizontal portions from above thealternating stack (32, 42) and at the bottom of each memory opening 49.A horizontal portion of the semiconductor channel layer is removed overa bottom surface of each memory opening 49. An opening is formed in thememory film layer at a bottom portion of each memory opening 49.

Each remaining annular portion of the memory film layer constitutes amemory film 50, which can have the same stacked structure and materialcompositions as in the first and second embodiments. Each remainingannular portion of the semiconductor channel layer constitutes asemiconductor channel 60, which includes a semiconductor material suchas at least one elemental semiconductor material, at least one III-Vcompound semiconductor material, at least one II-VI compoundsemiconductor material, at least one organic semiconductor material, orother semiconductor materials known in the art. In one embodiment, thesecond semiconductor channel layer 602L includes amorphous silicon orpolysilicon. A cavity 49′ can be present within a volume of each memoryopening 49 that is not filled with a memory film 50 and a semiconductorchannel 60. An annular horizontal portion of the memory film 50 canunderlie the semiconductor channel 60 within each memory opening. A topsurface of the conductive material layer 14 can be physically exposed atthe bottom of each cavity 49′. The semiconductor channel 60 iselectrically isolated from the substrate 10 by the memory film 50 withineach memory opening. Each memory film 50 can be topologicallyhomeomorphic to a torus. Each memory film 50 can be topologicallyhomeomorphic to a torus. As used herein, an element is homeomorphic to ageometrical shape if the shape of the element can be mapped to thegeometrical shape by continuous deformation without creation ordestruction of any hole.

Referring to FIG. 22, back gate dielectrics 66 can be formed on theinner sidewalls of the semiconductor channels 60 inside each memoryopening. In one embodiment, the back gate dielectrics 66 can be formedby depositing a back gate dielectric layer in the memory openings andover the alternating stack (32, 42), and by anisotropically etching theback gate dielectric layer. An opening is formed through each horizontalportion of the back gate dielectric layer at a bottom portion of eachmemory opening. Each remaining vertical portion of the back gatedielectric layer constitutes a back gate dielectric 66.

The back gate dielectrics 66 include at least one dielectric material.The dielectric materials that can be included in the back gatedielectrics 66 include, but are not limited to, silicon oxide, siliconnitride, a dielectric metal oxide, an organosilicate glass, or acombination thereof. In one embodiment, the back gate dielectrics 66 caninclude a stack of a silicon oxide layer and a dielectric metal oxidelayer. In one embodiment, the back gate dielectrics 66 do not include acharge trapping material or a charge storage material (such as siliconnitride). The thickness of each back gate dielectric 66 can be in arange from 3 nm to 30 nm, although lesser and greater thicknesses canalso be employed. A bottom surface of each back gate dielectric 66 cancontact a top surface of the conductive material layer 14. An outersidewall of each back gate dielectric 66 can contact an inner sidewallof a semiconductor channel 60 and an inner sidewall of a memory film 50.Each back gate dielectric 66 can be topologically homeomorphic to atorus.

Referring to FIG. 23, back gate electrodes 68 can be formed within eachcavity 49′ that is laterally surrounded by a back gate dielectric 66. Atleast one conductive material can be deposited within each cavity 49′that is laterally enclosed by a back gate dielectric 66 and over thealternating stack (32, 42). The at least one conductive material caninclude, for example, a conductive metallic nitride liner material (suchas TiN, TaN, and/or WN) and a conductive fill material (such as anelemental metal (e.g., W), an intermetallic alloy, a doped semiconductormaterial, a metal-semiconductor alloy material, or a combinationthereof). The deposited conductive material can be removed from abovethe topmost surface of the alternating stack (32, 42) by a planarizationprocess. Chemical mechanical planarization (CMP) and/or a recess etchprocess can be employed for the planarization process.

The remaining portion of the deposited conductive material can bevertically recessed, for example, by a recess etch below a horizontalplane including the top surface of the alternating stack (32, 42). Therecess depth below the horizontal plane including the top surface of thealternating stack (32, 42) can be in a range from 3 nm to 300 nm,although lesser and greater recess depths can also be employed. Eachremaining portion of the deposited conductive material constitutes aback gate electrode 68. Each back gate electrode 68 can be in contactwith the conductive material layer 14.

In one embodiment, the top surface of each back gate electrode 68 can beformed above a horizontal plane including the top surface of the topmostsacrificial material layer 42 within the alternating stack (32, 42). Inone embodiment, a top portion of each back gate dielectric 66 can becollaterally recessed vertically during the vertical recessing of thedeposited conductive material to form the back gate electrodes 68. Inanother embodiment, the recessing of the deposited conductive materialto form the back gate electrodes 68 can be performed selective to thedielectric material of the back gate dielectrics 66, i.e., withoutsubstantially etching the dielectric material of the back gatedielectrics 66. In this case, the top surface of each back gateelectrode 68 can be recessed below the horizontal plane including thetopmost surface of the alternating stack (32, 42).

In one embodiment, electrical dopants, which can be p-type dopants orn-type dopants, can be introduced into an upper portion of eachsemiconductor channel 60 to convert each implanted portion into a drainregion 63. A drain region 63 can be formed on top a remaining portion ofa semiconductor channel 60. Each drain region 63 can be an annularstructure, i.e., can be topologically homeomorphic to a torus. Eachdrain region 63 can contact an inner sidewall of a memory film 50, andmay contact a topmost portion of an outer sidewall of a back gatedielectric 66.

A dielectric cap layer 67 can be deposited into the recesses within thememory openings and over the alternating stack (32, 42). The dielectriccap layer 67 includes a dielectric material, which can be the same as,or different from, a dielectric material contained within the back gatedielectrics 66. The dielectric cap layer 67 can include a material thatis different from the material of the sacrificial material layers 42. Inone embodiment, the dielectric cap layer 67 can include silicon oxide ora dielectric metal oxide such as aluminum oxide. Optionally, the topsurface of the dielectric cap layer 67 can be planarized. The dielectriccap layer 67 can contact an inner sidewall and a top surface of eachdrain region 63, a top surface of each back gate dielectric 66, and atop surface of each back gate electrode 68.

Each set of a memory film 50 and a semiconductor channel 60 within amemory opening constitutes a memory stack structure 55 including aplurality of charge storage elements. A back gate electrode 68 and a setof nested layers laterally surrounding the back gate electrode 68 withina memory opening collectively constitute a pillar structure (68, 66, 60,63, 50). The set of nested layers include, from inside to outside, aback gate dielectric 66, a semiconductor channel 60, and a memory film50.

Referring to FIG. 24, a photoresist layer (not shown) can be appliedover the dielectric cap layer 67 and the alternating stack (32, 42), andcan be lithographically patterned to form openings therein. The patternin the photoresist layer can be transferred through the dielectric caplayer 67 and the alternating stack (32, 42) employing an anisotropicetch to form the at least one backside contact trench 79. Each backsidecontact trench 79 can extend through the entirety of the alternatingstack (32, 42), and can have a horizontal surface of the temporarymaterial layer 41 as a bottom surface. In one embodiment, theanisotropic etch can be selective to the material of the temporarymaterial layer 41, and the bottom surface of each backside contacttrench 79 can be coincident with the top surface of the temporarymaterial layer 41. In another embodiment, the bottom surface of abackside contact trench 79 can be located between a first horizontalplane including the topmost surface of the temporary material layer 41and the bottom surface of the temporary material layer 41. The sidewallsof each backside contact trench 79 can be substantially vertical ortapered. The photoresist layer can be subsequently removed, for example,by ashing.

Referring to FIG. 25, an etchant that selectively etches the secondmaterial of the sacrificial material layers 42 with respect to the firstmaterial of the insulator layers 32 and the temporary material layer 41can be introduced into the at least one backside contact trench 79, forexample, employing an etch process. Backside recesses are formed involumes from which the sacrificial material layers 42 are removed. Theremoval of the second material of the sacrificial material layers 42 canbe selective to the first material of the insulator layers 32, thematerial of the temporary material layer 41, and the material of theoutermost layer of the memory films 50. In an illustrative example, thesacrificial material layers 42 can include silicon nitride, the materialof the insulator layers 32 can be silicon oxide, and the material of thetemporary material layer 41 can be germanium, a silicon-germanium alloy,amorphous silicon, or polysilicon. In another embodiment, thesacrificial material layers 42 can include a semiconductor material suchas germanium, a silicon-germanium alloy, or silicon, the material of theinsulator layers 32 can include silicon oxide, and the material of thetemporary material layer 41 can include silicon nitride.

The etch process that removes the second material selective to the firstmaterial and the outermost layer of the memory films 50 can be a wetetch process employing a wet etch solution, or can be a gas phase (dry)etch process in which the etchant is introduced in a vapor phase intothe at least one backside contact trench 79. For example, if thesacrificial material layers 42 include silicon nitride, the etch processcan be a wet etch process in which the exemplary structure is immersedwithin a wet etch tank including phosphoric acid, which etches siliconnitride selective to silicon oxide, silicon, and various other materialsemployed in the art.

Each backside recess can be a laterally extending cavity having alateral dimension that is greater than the vertical extent of thecavity. In other words, the lateral dimension of each backside recesscan be greater than the height of the backside recess. A plurality ofbackside recesses can be formed in the volumes from which the secondmaterial of the sacrificial material layers 42 is removed. The memoryopenings in which the memory stack structures 55 are formed are hereinreferred to as front side openings or front side cavities in contrastwith the backside recesses. In one embodiment, the device regioncomprises an array of monolithic three-dimensional NAND strings having aplurality of device levels disposed above the substrate 10. In thiscase, each backside recess can define a space for receiving a respectiveword line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses can extend substantiallyparallel to the top surface of the substrate 10. The backside recess canbe vertically bounded by a top surface of an underlying insulator layer32 and a bottom surface of an overlying insulator layer 32. In oneembodiment, each backside recess can have a uniform height throughout.

A conductive material can be deposited in the plurality of backsiderecesses, on sidewalls of the at least one the backside contact trench79, and over the top surface of the dielectric cap layer 67. As usedherein, a conductive material refers to an electrically conductivematerial. The conductive material can be deposited by a conformaldeposition method, which can be, for example, chemical vapor deposition(CVD), atomic layer deposition (ALD), electroless plating,electroplating, or a combination thereof. The conductive material can bean elemental metal, an intermetallic alloy of at least two elementalmetals, a conductive nitride of at least one elemental metal, aconductive metal oxide, a conductive doped semiconductor material, aconductive metal-semiconductor alloy such as a metal silicide, alloysthereof, and combinations or stacks thereof. Non-limiting exemplaryconductive materials that can be deposited in the plurality of backsiderecesses include tungsten, tungsten nitride, titanium, titanium nitride,tantalum, and tantalum nitride. In one embodiment, the conductivematerial can comprise a metal such as tungsten and/or metal nitride. Inone embodiment, the conductive material for filling the plurality ofbackside recesses can be selected from tungsten and a combination oftitanium nitride and tungsten. In one embodiment, the conductivematerial can be deposited by chemical vapor deposition.

A plurality of electrically conductive layers 46 can be formed in theplurality of backside recesses, and a contiguous conductive materiallayer (not shown) can be formed on the sidewalls of each backsidecontact trench 79 and over the dielectric cap layer 67. Thus, at least aportion of each sacrificial material layer 42 can be replaced with anelectrically conductive layer 46, which is a conductive materialportion.

Subsequently, the deposited conductive material of the contiguousconductive material layer can be etched back from the sidewalls of eachbackside contact trench 79 and from above the dielectric cap layer 67,for example, by an isotropic etch. Each remaining portion of thedeposited conductive material in the backside recesses constitutes anelectrically conductive layer 46. Each electrically conductive layer 46can be a conductive line structure.

Each electrically conductive layer 46 can function as a combination of aplurality of control gate electrodes and a word line electricallyconnecting, i.e., electrically shorting, the plurality of control gateelectrodes. The plurality of control gate electrodes within eachelectrically conductive layer 46 can include control gate electrodeslocated at the same level for the vertical memory devices including thememory stack structures 55. In other words, each electrically conductivelayer 46 can be a word line that functions as a common control gateelectrode for the plurality of vertical memory devices.

Each memory stack structure 55 includes a memory film 50 and asemiconductor channel 60 within a memory opening. The total number ofcharge storage elements within a memory stack structure 55 can be thesame as the total number of levels of the control gate electrodes, whichcan be end portions of the electrically conductive layers 46, if eachcontrol gate electrode 46 laterally surrounds the entire periphery ofmemory stack structure 55. Alternatively, if more than one control gateelectrode is formed in proximity to a memory stack structure 55 at thesame level, the total number of charge storage elements at thecorresponding level of the memory stack structure 55 can be the same asthe total number of control gate electrodes 46 located in proximity tothe memory stack structure 55 at the corresponding level. If a total ofN control gate electrodes are located in proximity to the memory film 50at each level of the electrically conductive layers 46, the total numberof charge storage elements per memory film 50 can be the product of thetotal number of levels of the electrically conductive layer 46 and theinteger N.

Referring to FIG. 26, an insulating spacer 74 can be formed on thesidewalls of the backside contact trench 79 by depositing a contiguousdielectric material layer and anisotropically etching horizontalportions of the contiguous dielectric material layer. The insulatingspacer 74 includes a dielectric material, which can comprise, forexample, silicon oxide, silicon nitride, a dielectric metal oxide, adielectric metal oxynitride, or a combination thereof. The thickness ofthe insulating spacer 74, as measured at a bottom portion thereof, canbe in a range from 1 nm to 50 nm, although lesser and greaterthicknesses can also be employed. In one embodiment, the thickness ofthe insulating spacer 74 can be in a range from 3 nm to 10 nm. A cavity79′ is formed in a volume of each backside contact trench 79 that is notfilled with the insulating spacer 74.

Referring to FIG. 27, an etchant that selectively etches the material ofthe temporary material layer 41 with respect to the first material ofthe insulator layers 32 can be introduced into the at least one backsidecontact trench 79, for example, employing an etch process. A bottommostbackside cavity is formed in the volume from which the temporarymaterial layer 41 is removed. The bottommost backside cavity is hereinreferred to as a source-level backside recess 29. The source-levelbackside recess 29 is a backside cavity that is located at the sourcelevel, i.e., the level at which source regions are to be subsequentlyformed. In one embodiment, the removal of the material of the temporarymaterial layer 41 can be selective to the first material of theinsulator layers 32, and to the material of the insulating spacer 74.

The etch process that removes the material of the temporary materiallayer 41 selective to the first material can be a wet etch processemploying a wet etch solution, or can be a gas phase (dry) etch processin which the etchant is introduced in a vapor phase into the at leastone backside contact trench 79. For example, if the temporary materiallayer 41 includes silicon nitride, the etch process can be a wet etchprocess in which the exemplary structure is immersed within a wet etchtank including phosphoric acid, which etches silicon nitride selectiveto silicon oxide, silicon, and various other materials employed in theart. In another example, if the temporary material layer 41 includesgermanium or a silicon-germanium alloy, the etchant can include acombination of hydrogen peroxide and dilute hydrofluoric acid.

Referring to FIG. 28, a portion of each memory film 50 physicallyexposed to the source-level backside recess 29 can be removed by atleast one etch process, which can be a series of isotropic etchprocesses. The chemistry of each isotropic etch process can be selectedto sequentially remove the various materials of the memory films 50 fromoutside to inside. If each memory film 50 includes at least one blockingdielectric 502, a charge storage region 504, and a tunneling dielectric505 as in the first and second embodiments, a first isotropic etchprocess can etch a portion of the at least one blocking dielectric 502,a second isotropic etch process can etch a portion of the charge storageelement 504, and a third isotropic etch process can etch a portion ofthe tunneling dielectric 505. The isotropic etch process that etches thematerial of the tunneling dielectric 505 can be selective to thematerial of the semiconductor channels 60. An annular dielectricmaterial portion 50A that includes a remaining portion of the memoryfilm 50 can be formed underneath each source region 30. The annulardielectric material portion 50A provides electrical isolation between asource region 30 and the underlying patterned conductive material layer14.

Subsequently, electrical dopants can be introduced through the cavity79′ and into the physically exposed portion of the sidewall of eachsemiconductor channel 60. The electrical dopants can be p-type dopantsor n-type dopants. Exemplary p-type dopants include B, Ga, and In.Exemplary n-type dopants include P, As, and Sb. Each portion of thesemiconductor channel 60 into which the electrical dopants areintroduced is converted into a source region 30.

The electrical dopants can be introduced into physically exposedportions of the semiconductor channels 60 by a plasma doping processand/or a gas phase doping process. If a plasma doping process isemployed, the exemplary structure can be placed in a process chamber inwhich a plasma of the electrical dopants is generated. Non-limitingexamples of process gases from which the plasma can be generated includeB₂H₆, PH₃, AsH₃, and SbH₃. In a gas phase doping process, the exemplarystructure is placed in a process chamber, and is subjected to a dopantgas at an elevated temperature, which can be, for example, in a rangefrom 600 degrees Celsius to 1,000 degrees Celsius. The atomicconcentration of the electrical dopants in each source region 30 can bein a range from 1.0×10¹⁹/cm³ to 1.0×10²¹/cm³, although lesser andgreater atomic concentrations can also be employed.

Within each memory opening, the source region 30 can have a samehorizontal cross-sectional shape and areas as the overlyingsemiconductor channel 60. The source region 30 includes the samesemiconductor material as the remaining portions of the semiconductorchannel 60, and further includes the electrical dopants. In oneembodiment, the composition of the source regions 30 can differ from thecomposition of the semiconductor channel 60 by the presence of theelectrical dopant atoms in the source region 30, while the semiconductorchannel 60 is substantially free of the electrical dopants or doped withelectrical dopants of opposite conductivity dopants than the sourceregion 30. Further, the composition of drain region 63 can differ fromthe composition of the semiconductor channel 60 by the presence of theelectrical dopant atoms in the drain region 63, while the semiconductorchannel 60 is substantially free of the electrical dopants or doped withelectrical dopants of opposite conductivity dopants than the sourceregion 30. In one embodiment the source region 30 and the drain region63 within a same memory opening can have a same lateral thickness, andcan have a substantially same horizontal cross-sectional area. Thesource regions 30 and the drain regions 63 can have a same type ofdoping. For example, the source regions 30 and the drain regions 63 canbe n-doped, or the source regions 30 and the drain regions 63 can bep-doped. The semiconductor channel 60 can be p-doped, n-doped, orintrinsic.

Referring to FIGS. 29A and 29B, a conductive material can be depositedin the source-level backside recess 29 and the cavity 79′ within thebackside contact trench 79, and over the top surface of the dielectriccap layer 67. The conductive material can be deposited by a conformaldeposition method, which can be, for example, chemical vapor deposition(CVD), atomic layer deposition (ALD), electroless plating,electroplating, or a combination thereof. The conductive material can bean elemental metal, an intermetallic alloy of at least two elementalmetals, a conductive nitride of at least one elemental metal, aconductive metal oxide, a conductive doped semiconductor material, aconductive metal-semiconductor alloy such as a metal silicide, alloysthereof, and combinations or stacks thereof. In one embodiment, theconductive material can comprise a metal such as tungsten and/or metalnitride. In one embodiment, the conductive material for filling thesource-level backside recess 29 and the cavity 79′ within the backsidecontact trench 79 can be selected from tungsten and a combination oftitanium nitride and tungsten. In one embodiment, the conductivematerial can be deposited by chemical vapor deposition.

An excess portion of the conductive material deposited over the topsurface of the dielectric cap layer 67 can be removed by a planarizationprocess, which can be a chemical mechanical planarization (CMP) processand/or a recess etch process. A source electrode 26 can be formed ineach source-level backside recess 29, and a backside contact viastructure 76. Each source electrode 26 contacts a source region 30. Eachsource electrode 26 is formed directly on a source region 30 and anannular dielectric material portion 50A. A source electrode 26 canlaterally surrounds a source region 30 and contact and entire outerperiphery of the source region 30.

A dielectric material portion including an annular unetched portion 50Aof a memory film 50 can be present between the source region 30 and anunderlying conductive material layer 14. A plurality of conductivematerial layers 14 can be provided. A conductive material layer 14 canunderlie a single memory stack structure 55, a plurality of memory stackstructures 55 located between a neighboring pair of backside contact viastructures 76, or a plurality of memory stack structures 55 that arelocated within an area including more than two backside contact viastructures 76. The width of each contiguous portion of a conductivematerial layer 14 can correspond to the width of a word line finger Fbetween a neighboring pair of backside contact via structures 76, or cancorrespond to the width of a block B including multiple backside contactvia structures 76.

Referring to FIGS. 30A and 30B, a contact cavity including a set ofstepped surfaces can be formed within a contact region 300 of the thirdexemplary structure, for example, by repetition of a verticalanisotropic etch process and a horizontal opening expansion process(such as trimming) The contact region 300 is adjacent to a device region100 that includes memory stack structures in memory openings and thebackside contact via structures 46. The contact cavity can be filledwith a retro-stepped dielectric material portion 65, which is adielectric material portion of which the lateral extent is greater atlevels farther away from the substrate 10 than at levels proximal to thesubstrate 10. The retro-stepped dielectric material portion 65 can beformed by deposition of a dielectric material such as silicon oxide,organosilicate glass, silicon nitride, or a combination thereof into thecontact cavity, and removing an excess portion of the depositeddielectric material from above a horizontal plane including the topsurface of the dielectric cap layer 67 by a planarization process. Theplanarization process can employ a chemical mechanical planarizationprocess (CMP) or a recess etch process.

A via level dielectric layer 70 can be formed over the dielectric caplayer 67 and the backside contact via structures 76. The via leveldielectric layer 70 includes an interlayer dielectric material such assilicon oxide, silicon nitride, and organosilicate glass. The thicknessof the via level dielectric layer 70 can be in a range from 30 nm to1,000 nm, although lesser and greater thicknesses can also be employed.

Various contact via structures can be formed through the via leveldielectric layer 70 and underlying material layers. The various contactvia structures can include at least one source contact via structure 179that contacts the top surface of a backside contact via structure 76,and drain contact via structures 73 contacting top surfaces of the drainregions 63. The depth of each via cavity for the drain contact viastructures 73 can be controlled such that the bottom surfaces of the viacavities for the drain contact via structures 73 are formed above thetopmost surfaces of the back gate electrodes 68. Each remaining portionof the dielectric cap layer 67 that remains over a gate electrode 68 isherein referred to as a dielectric cap portion 67C. Each dielectric capportion 67C has the same composition as the remaining portion of thedielectric cap layer 67 that are present over the alternating stack (32,46) of insulator layers 32 and the electrically conductive layers 46. Abottom surface of a drain contact via structure 73 can contact a topsurface of a dielectric cap portion 67C and an annular top surface of adrain region 63. A top surface of a back gate electrode 68 can contact abottom surface of dielectric cap portion 67C.

Additional contact via structures (8C, 14C) can be formed through thevia level dielectric layer 70, one of the dielectric cap layer 67 andthe retro-stepped dielectric material portion 65, and to a top surfaceof an electrically conductive layer 46 or the at least one conductivematerial layer 14. Each control electrode contact via structure 8C cancontact, or can be electrically shorted to, an electrically conductivelayer 46, and electrically isolated from the source electrodes 26 andother the electrically conductive lines 46 located at different levels.Each back gate contact via structure 14C can contact, or can beelectrically shorted to, the at least one conductive material layer 14,and electrically isolated from the source electrodes 26 and theelectrically conductive lines 46. The back gate contact via structure14C and the conductive material layer 14 provide an electricallyconductive path to the back gate electrodes 68 so that a backside biasvoltage can be applied during operation of each memory stack structure.In one embodiment, the additional contact via structures (8C, 14C) maybe formed in the same deposition step by deposition of a same conductivematerial and removal of excess portions of the deposited conductivematerial from a top surface of the via level dielectric layer 70.

A line level dielectric layer 80 can be formed over the via leveldielectric layer 70. The line level dielectric layer 80 includes aninterlayer dielectric material such as silicon oxide, silicon nitride,and organosilicate glass. The thickness of the line level dielectriclayer 80 can be in a range from 30 nm to 1,000 nm, although lesser andgreater thicknesses can also be employed.

Various conductive line structures (83, 86, 88) can be formed throughthe line level dielectric layer 80. The various conductive linestructures (83, 86, 88) can include at least one source line 86 thatcontacts a top surface of a contact via structure 79, and at least onedrain line 83 (i.e., a bit line) that contacts a top surface of a draincontact via structures 73, and gate control lines 88 contacting arespective control electrode contact via structure 8C, and a back gatecontrol line 89 that contacts the back gate contact via structure 14C.

The third exemplary structure is a monolithic three-dimensional memorystructure that comprises a stack (32, 46) including an alternatingplurality of insulator layers 32 and electrically conductive layers 46,a memory opening 49 extending through the stack (32, 46), and a pillarstructure (68, 66, 60, 63, 30, 50) located within the memory opening andcomprising a back gate electrode 68 and a set of nested layers laterallysurrounding the back gate electrode 68. The set of nested layersinclude, from inside to outside, a back gate dielectric 66, asemiconductor channel 60, and a memory film 50. A patterned conductivematerial layer 14 can contact a bottom surface of the back gateelectrode 68. The patterned conductive material layer 14 can beelectrically isolated from the semiconductor channel 60.

The third exemplary structure can further comprise an annular dielectricmaterial portion 50A having a same composition as the memory film 50 andcontacting an outer sidewall of the back gate dielectric 66. Thepatterned conductive material layer 14 can contact a bottom surface ofanother back gate electrode 68 located within another memory openingthrough the stack (32, 46). A dielectric material portion 13 can beembedded within an upper portion of the substrate 10, and can contact abottom surface of the patterned conductive material layer 14.

A dielectric cap portion 67C can contact a top surface of the back gateelectrode 68, and a drain region 63 can contact a top surface of thesemiconductor channel 60 and a surface of the dielectric cap portion67C. The drain region 63 can have an annular shape, and can contact asidewall of the dielectric cap portion 67C.

A source region 30 can be adjoined to a bottom portion of thesemiconductor channel 60, and can laterally surround a portion of theback gate dielectric 66. A source electrode 26 can contact, andlaterally surround, the source region 30. The source electrode 26 islocated over the substrate 10. The source electrode 26 can underlie thealternating stack (32, 46), and a backside contact via structure 76 canextend through the alternating stack (32, 46) and can contact the sourceelectrode 26. In one embodiment, the source region 30 can have a samehorizontal cross-sectional shape as the semiconductor channel 60, andcan be laterally spaced from the back gate electrode 68 by the back gatedielectric 66.

Referring to FIG. 31, an alternate embodiment of the third exemplarystructure is illustrated, which can be derived from the third exemplarystructure by omitting the processing step employed to convert topportions of the semiconductor channels 60 to drain regions 63 byintroduction of electrical dopants as illustrated in FIG. 23. Thus, thedrain regions 63 are not present within the various in-processstructures between the processing steps of FIGS. 23-29B. After formationof the via level dielectric layer 70 and via cavities therethrough, atop surface of each semiconductor channel 60 is physically exposed atbottom surfaces of the various via cavities. A doped semiconductormaterial can be deposited within the via cavities and over the via leveldielectric layer 70. The deposited doped semiconductor material can bepatterned, for example, by a planarization process, which can employchemical mechanical planarization (CMP) and/or a recess etch. Remainingportions of the doped semiconductor material can form drain regions 163.Each drain region 163 contacts a top surface of a semiconductor channel60. The dielectric cap portion 67C can contact a bottom surface of thedrain region 63 and an inner sidewall of the semiconductor channel 60.

In the alternate embodiment of the third exemplary structure, eachdielectric cap portion 67C can be formed over a back gate electrode 68and on an inner sidewall of a semiconductor channel 60. Each drainregion 163 can be formed over, and on the top surface of, a dielectriccap portion 67C and on a top surface of a semiconductor channel 60 bydepositing and patterning a doped semiconductor material. Additionalstructures, such as the line level dielectric layer 80 and theconductive line structures (83, 86, 88), can be formed as in the thirdexemplary structure illustrated in FIGS. 30A and 30B.

In one embodiment, each of the first, second, and third exemplarystructures can be formed on a semiconductor substrate such as a siliconsubstrate. Each of the first, second, and third exemplary structures isa multilevel structure including a stack {(32, 142) or (32, 46)} of analternating plurality of electrically conductive layers (142 or 46) andinsulator layers 32 located over a semiconductor substrate including thesemiconductor material layer. An array of memory stack structures 55 canbe located within memory openings through the stack {(32, 142) or (32,46)}.

In one embodiment, the device located on the semiconductor substrate caninclude a vertical NAND device located in the device region 100, and atleast one of the electrically conductive layers (142 or 46) in the stack{(32, 142) or (32, 46)} can comprise, or can be electrically connectedto, a word line of the NAND device. The device region can include aplurality of semiconductor strip structures 160. At least one endportion of each of the plurality of semiconductor strip structures 160extends substantially perpendicular to a top surface of thesemiconductor substrate. The device region further includes a pluralityof charge storage elements located within each charge trapping layer504. Each charge storage element is located adjacent to a respective oneof the plurality of semiconductor strip structures 160. The deviceregion further includes a plurality of control gate electrodes having astrip shape extending substantially parallel to the top surface of thesubstrate 10. The plurality of control gate electrodes comprise at leasta first control gate electrode located in the first device level and asecond control gate electrode located in the second device level. Theplurality of electrically conductive layers (142 or 46) in the stack{(32, 142) or (32, 46)} can be in electrical contact with, or cancomprise, the plurality of control gate electrodes, and extends from thedevice region to a contact region including a plurality of electricallyconductive contact via structures.

In case the exemplary structure includes a three-dimensional NANDdevice, a stack {(32, 142) or (32, 46)} of an alternating plurality ofword lines (142 or 46) and insulating layers 32 can be located over asemiconductor substrate. Each of the word lines (142 or 46) andinsulating layers 32 is located at different levels that are verticallyspaced from a top surface of the semiconductor substrate by differentdistances. An array of memory stack structures 55 is embedded within thestack {(32, 142) or (32, 46)}. Each memory stack structure 55 comprisesa semiconductor strip structure 160 and at least one charge storageelement 50 located adjacent to the semiconductor strip structure 160. Atleast one end portion of the semiconductor strip structure 160 extendssubstantially perpendicular to the top surface of the semiconductorsubstrate through the stack {(32, 142) or (32, 46)}.

In a non-limiting illustrative example, the insulating layers 32 cancomprise silicon oxide layers, the plurality of word lines (142 or 46)can comprise doped semiconductor material, tungsten, or a combination oftitanium nitride and tungsten, the at least one charge storage element50 can comprise a tunneling dielectric, a blocking dielectric layer, andeither a plurality of floating gates or a charge trapping layer locatedbetween the tunneling dielectric layer and the blocking dielectriclayer. An end portion of each of the plurality of word lines (142 or 46)in a device region can comprise a control gate electrode locatedadjacent to the at least one charge storage element. A plurality ofcontact via structures contacting the word lines (142 or 46) can belocated in a contact region. The plurality of word lines (142 or 46)extends from the device region 100 to the contact region 300. A drainline 83, as embodied as a conductive line structure that contacts atleast one drain contact via structure 73 or at least one drain region163, can electrically contact an upper portion of the semiconductorstrip structure 160. As used herein, a first element “electricallycontacts” a second element if the first element is electrically shortedto the second element.

In the first exemplary semiconductor structure, the electrical currentbetween a first contact via structure and a second contact via structurelocated above an alternating stack (32, 142) is controlled by theelectrical charges that are stored at various charge storage elementswithin the memory film 50, and by the electrical bias voltage that isapplied to the back gate electrode 168 that is adjacent to a U-shapedsemiconductor channel within a semiconductor strip structure 160. Thefirst contact via structure can function as a source contact viastructure, and the second contact via structure can function as a draincontact via structure.

In the second exemplary semiconductor structure, the electrical currentbetween a source contact via structure and a drain contact via structureis controlled by the electrical charges that are stored at variouscharge storage elements of the memory film 50, and by the electricalbias voltage that is applied to the back gate electrode 68 that isadjacent to a semiconductor channel (which can be a vertical portion ofthe semiconductor strip structure 160) located between a source linelayer 12 and the drain contact via structure.

In the third exemplary semiconductor structure, the electrical currentbetween a source contact via structure 79 and a drain contact viastructure 73 is controlled by the electrical charges that are stored atvarious charge storage elements of the memory film 50, and by theelectrical bias voltage that is applied to the back gate electrode 68that is adjacent to a semiconductor channel 60 located between thesource region 30 and the drain region (63 or 163).

In one embodiment, each portion of the memory film 50 adjacent to an endportion of a conductive material layer (which can be a second materiallayer 142 in case the second material layers 142 are formed asconductive material layers, or a layer of a conductive material thatreplaces a sacrificial material of the second material layers 142 incase the second material layers 142 are initially formed as sacrificialmaterial layers, or electrically conductive layers 46) can function as acharge storage element. In one embodiment, each charge storage elementcan be a portion of a charge trapping material that is present withinthe memory film 50. For example, each charge storage element can be acharge trapping material that is present in a charge trapping layer 504.

A charge storage element can be present at each end of control gateelectrodes, which can be end portions of the conductive material layerswithin the alternating stack. In one embodiment, only a single controlgate electrode can be provided per level within each memory stackstructure. In another embodiment, two or more control gate electrodescan be provided within the same level in each memory stack structure. Inone embodiment, two or more control gate electrodes can be provided ateach level in each memory stack structure.

In one embodiment, at least one of the charge storage elements may beconfigured to store more than one amount of non-zero total electricalcharge. In other words, a charge storage element can be configured tostore no electrical charge, a first amount of electrical charge that isnot zero, a second amount of electrical charge that is not zero anddifferent from the first amount, and optionally an i-th amount ofelectrical charge for every integer i that is greater than 2 and notexceeding the maximum integer n that is greater than 2.

In one embodiment, a predefined set of stored electrical charge amountcan be defined for each of the charge storage elements. In oneembodiment, a common predefined set of stored electrical charge amountscan be employed for all of the charge storage elements. To detect theamount of electrical charges stored at a particular charge storageelement as embodied as a portion of the charge trapping layer 504, thecontrol gate electrode adjacent to the selected charge storage element(which is located adjacent to a semiconductor channel portion) can beelectrically biased at different test voltages while all other controlgate electrodes adjacent to the semiconductor channel portion can beelectrically biased at a voltage that turns on the semiconductor channelportion irrespective of the electrical charges stored in other chargestorage elements. Multiple test voltages are sequentially applied to theselected charge storage element to determine a channel-turn-on triggervoltage that is required to turn on the semiconductor channel portion.The amount of the electrical charge stored in the selected chargestorage element can be determined from the measured channel-turn-ontrigger voltage. In one embodiment, the relationship between themeasured channel-turn-on trigger voltage and the amount of storedelectrical charges can be calibrated in a test environment, and the dataon the relationship can be stored in a permanent (e.g., non-volatile)memory module and retrieved at the time of measurement of thechannel-turn-on trigger voltage.

In one embodiment, the relationship between the measured channel-turn-ontrigger voltage and the amount of stored electrical charges can bedigitized so that the data stored in each charge storage element canindicate a k-nary bit data in which k is greater than 2. For example, ifeach charge storage element can store no electrical charge and twonon-zero amounts of electrical charges, k is 3, and each charge storageelement can store a ternary bit, of which the content can be “0,” “1,”or “2.” If each charge storage element can store no electrical chargeand three non-zero amounts of electrical charges, k is 4, and eachcharge storage element can store a quaternary bit, of which the contentcan be “0,” “1,” “2,” or “3.” If each charge storage element can storeno electrical charge and (n−1) non-zero amounts of electrical charges, kis n, and each charge storage element can store an n-ary bit (i.e., abit with the arity of n), of which the content can be “0,” “1,” “2,” . .. “n−2,” or “n.”

In one embodiment, the first exemplary structure includes a monolithicthree-dimensional memory structure comprising a stack including analternating plurality of insulator layers 32 and electrically conductivelayers (which can be the second material layers (46 or 142) orconductive material layers formed by replacement of the sacrificialmaterial of the second material layers 142 in case the second materiallayers 142 initially include the sacrificial material) and located overa substrate 10, a trench (e.g., a line trench 149 illustrated in FIGS.3A and 3B) extending through the stack to a top surface of the substrate10 and including a first sidewall and a second sidewall that arelaterally spaced from each other, and a plurality of semiconductor stripstructures 160 straddling the trench. Each semiconductor strip structure160 contacts a respective portion of the first sidewall and a respectiveportion of the second sidewall and is laterally spaced from one anotheralong the first horizontal direction. A back gate dielectric 166contacts inner sidewalls of the plurality of semiconductor stripstructures 160. A back gate electrode 168 contacts inner sidewalls ofthe back gate dielectric 166.

Referring to FIG. 32, a schematic circuit diagram for athree-dimensional memory device including one of the memory stackstructures of the present disclosure is shown. The three-dimensionalmemory device can include a vertical string of N memory cells (MC1, MC2,MCS, . . . , MCN) that are vertically stacked and sharing a samesemiconductor channel. Each memory cell includes a set of at least onecharge storage element CSE, which can be a portion of a charge trappinglayer 504 located at a respective level. A control gate electrode (CG1,CG2, CGS, . . . , CGN), which can be an end portion of a conductivematerial layer, can be capacitively coupled to each set of at least onecharge storage element CSE. While only a single charge storage elementand a single control gate electrode is illustrated in FIG. 32,embodiments are expressly contemplated herein in which multiple chargestorage elements and/or multiple control gate electrodes located on asame semiconductor channel and at a same level.

Optionally, at least one source select gate transistor including asource select gate (SGS) electrode and/or at least one drain select gatetransistor including a drain select gate (SGD) electrode can be formedat end portions of the vertical string of N memory cells (MC1, MC2, MCS,. . . , MCN). The vertical string can be in a U-shaped configuration asillustrated in the first exemplary structure (in which N/2 levels ofconductive line structures are provided as control gate electrodes), orcan be in a linear configuration as illustrated in the second and thirdexemplary structures. The source-side end of the vertical string can beelectrically shorted to a source line SL, and the drain-side end of thevertical string can be electrically shorted to a drain line DL. The backgate electrode BG extends through the entirety of the N memory cells(MC1, MC2, MCS, . . . , MCN), and can apply a same backside bias voltageto each of the N memory cells.

According to an aspect of the present disclosure, presence of a backgate electrode (68 or 168) in a three-dimensional memory structure canbe utilized to program, and to sense, “multinary” bits at a single levelwithin a memory stack structure 55. As used herein, a “multinary” bitrefers to a bit that can store more than two states, i.e., a k-nary bitin which k is an integer not less than 3. The three-dimensional memorydevice can comprise a stack including an alternating plurality ofinsulator layers and electrically conductive layers that include controlgate electrodes located at their respective level, a plurality of chargestorage elements located in the stack, a semiconductor channel locatedon a first side of the plurality of charge storage elements and withinthe stack, and a back gate electrode located on a second side of theplurality of charge storage elements and within the stack.

A set of at least one charge storage element located at a selected levelSL of the stack can be programmed by injecting electrical charges intothe set of at least one charge storage element by selecting a mode ofprogramming from among a plurality of modes of programming. Each set ofat least one charge storage element can store a multinary bit, and thus,can function as a multinary bit storage unit. The total amount ofelectrical charge stored within the set of at least one charge storageelement is a function of the selected mode of programming that isselected from among a plurality of modes of programming. The set of atleast one charge storage element can include a single charge storageelement such as a portion of a charge trapping layer 504, or can includea plurality of charge storage elements such as multiple portions of asingle charge storage layer 504 that adjoin different control gateelectrodes, or multiple charge storage layers 504 placed in proximity toa common semiconductor channel and multiple control gate electrodes. Theplurality of modes of programming can inject electrical charges to aselected subset of charge storage elements from among a plurality ofcharge storage elements located at a selected level SL, or can injectdifferent amounts of electrical charges to a charge storage element orto a plurality of charge storage elements by selecting suitableprogramming conditions, e.g., the electrical bias voltage between thecontrol gate electrode(s) and the semiconductor channel in proximity tothe selected set of at least one charge storage element.

The charged state of the set of at least one memory element, i.e., thestored value of the multinary bit in the corresponding multinary bitstorage unit, can be determined by measuring electrical current throughthe semiconductor channel under a plurality of electrical biasconditions. The variables within the plurality of electrical biasconditions include at least one of the backside bias voltage applied tothe back gate electrode and the control gate bias voltage applied to thecontrol gate electrode(s) located at the selected level SL and adjoiningthe selected set of at least one memory element. In one embodiment, eachof the plurality of electrical bias conditions differs from one anotherby at least one of a value for a backside bias voltage applied to theback gate electrode and a value for a control gate bias voltage appliedto a control gate electrode located at the selected level SL.

For any selected set of at least one charge storage element, which islocated at a respective level within a respective memory stackstructure, electrical current through the semiconductor channel that ismost proximal to the selected set of at least one charge element can bemeasured under a plurality of bias voltage conditions, within which atleast one of a value for a backside bias voltage applied to the backgate electrode and a value for a control gate bias voltage applied to acontrol gate electrode located at the selected level SL. If a pluralityof control gate electrodes are located on the at least one chargeelement, each control gate bias voltage applied to a respective controlgate electrode among the plurality of control gate electrodes can be aparameter. In this case, each set of bias voltage conditions comprises acombination of respective values for the control gate voltages for theplurality of control gate electrodes and a value for the backside biasvoltage.

Each bias voltage condition can include a value for a backside biasvoltage that is applied to a back gate electrode that is most proximalto the selected set of at least one charge storage element, and at leastone selected control gate bias voltage that is applied to a respectivecontrol gate electrode that is proximal to the selected at least onecharge storage element. Unselected control gate electrodes that arelocated at different levels than the level at which the selected set ofat least one charge storage element is present can be electricallybiased at an unselect control gate bias voltage, which is selected toturn on the portion of the semiconductor channel located at thecorresponding level. Thus, under each of the plurality of electricalbias conditions that are employed to measure the electrical currentthrough the semiconductor channel, the control gate electrodes locatedat levels different from the selected level SL can be electricallybiased at voltages that, in conjunction with a respective backside biasvoltage within the respective electrical bias conditions, turn onportions of the semiconductor channel located at each level differentfrom the selected level SL. The voltage bias applied to the control gateelectrodes located at levels different from the selected level SL isherein referred to as an “unselect control gate bias voltage.”

For example, a set of at least one charge storage element can storeelectrical charges in k different states such that k is an integergreater than 2. In other words, the set of at least one charge storageelement can store a k-nary data, and the value of the k-nary data can beretrieved from the set of at least one charge storage element if thetotal amount of electrical charge that is stored in the set of at leastone charge storage element can be determined. The set of at least onecharge storage element can be in a state selected from k possiblestates, each of which has different total amount of store electricalcharges. For example, a first state can be a state in which the totalamount of stored electrical charges is zero, a second state can be astate in which the total amount of stored electrical charges is anon-zero quantity, and i-th state can be a state in which the totalamount of stored electrical charges can be a non-zero quantity that isdifferent from any of the non-zero quantities corresponding to the firstthrough (i−1)-th states for each value of i that is greater than 2 andnot exceeding k. In one embodiment, the value for total amount of storedelectrical charges for an i-th state can be greater than any of thevalues for the total amount of stored electrical charges correspondingto the first through (i−1)-th states for each value of i that is greaterthan 2 and not exceeding k.

The operation of the semiconductor channel during the various electricalcurrent measurement steps is illustrated in FIG. 33. An alternatingstack (32, 46) of insulator layers 32 and conductive material layers 46,i.e., electrically conductive layers, can be provided within any of thefirst, second, and third exemplary structures of the present disclosure.A memory film 50 including a blocking dielectric 502, a charge storagelayer 504, and a tunneling dielectric 505 can be formed on a sidewall ofthe alternating stack (32, 46). A semiconductor channel 60, a back gatedielectric 66, and a back gate electrode 68 can be present on thesemiconductor channel 60 according to any of the embodiments of thepresent disclosure.

A selected set of at least one charge storage element 51 can be aportion of a charge trapping layer 504, and can include storedelectrical charges such as electrons. At least one control gateelectrode located at the selected level SL including the selected set ofat least one charge storage element 51 and in proximity to the selectedset of at least one charge storage element 51 is represented as aselected control gate electrode 46-S. A control gate bias voltage can beapplied to the selected control gate electrode 46S. The unselect controlgate bias voltage can be applied to each of the unselected control gateelectrodes 46-US, which include all control gate electrodes that arelocated at unselected levels USL, which are different from the selectedlevel SL in which the selected set of at least one charge storageelement 51 is present.

The magnitude of the unselect control gate bias voltage can bedetermined such that, in conjunction with the backside bias voltage, theapplied unselect control gate bias voltage turn on each portion of thesemiconductor channel 60 that is not at the selected level SL. In otherwords, for any selected value for the backside bias voltage, theunselect control gate bias voltage is selected such that portions of thesemiconductor channel 60 that are located at the unselected level USLincluding the unselected control gate electrodes 46-US becomeconductive. In one embodiment, a low bias voltage (e.g., a bias voltageabout zero volt) can be applied to the unselected control gateelectrodes to reduce read disturb. For the portions of the semiconductorchannel under the unselected control gate electrodes (i.e., at theunselected levels USL), the positive back gate bias voltage applied tothe back gate electrode can turn on the portions of the semiconductorchannel near the back gate electrode to allow the flow of the electricalcurrent. For example, in case electrons are the minority charge carriersthat conduct electricity in a p-doped semiconductor channel, andelectrons are stored in the charge storage elements 51, the portions ofthe semiconductor channel 60 that are located at the unselected levelsUSL of the unselected control gate electrodes 46-US can containelectrons as charge carriers. This property is illustrated by anon-depleted channel portion 60ND, which includes all portions of thesemiconductor channel 60 in which electrons are present to enable chargeconduction therethrough. In one embodiment, a positive bias voltage toattract electrons into the backside (the inner side) of thesemiconductor channel 60 can be applied to the back gate electrode 68.

A negative voltage, a zero voltage, or a positive voltage of a lowmagnitude than the high positive voltage applied to the unselectedcontrol gate electrodes 46-US can be applied to the selected controlgate electrode 46-S. In one embodiment, the control gate bias voltageapplied to the selected control gate electrode 46-S can be negative. Ingeneral, the control gate bias voltage applied to the selected controlgate electrode 46-S can be selected such that the semiconductor channel60 becomes conducting or non-conducting depending on the total amount ofelectrical charges present at the selected set of at least one chargestorage element 51 (located at the same level (i.e., the selected levelSL) as the selected control gate electrode 46-S). For example, acombination of the positive voltage applied to the back gate electrode68 and a control gate bias voltage applied to the selected control gateelectrode 46-S can be selected such that the portion of thesemiconductor channel 60 at the selected level SL conducts electricallyif the at least one charge storage element 51 includes less than apreset amount of electrons, and does not conduct electrically if the atleast one charge storage element 51 includes more than the preset amountof electrons. In other words, the electrical field generated by thecombination of the control gate bias voltage applied to the selectedcontrol gate electrode 46-S and any stored electrical charge in the atleast one charge storage element 51 at the selected level SL causes theportion of the semiconductor channel 60 at the selected level SL eitherto conduct or not to conduct depending on the total amount of storedelectrical charge in the at least one charge storage element 51.

Voltages applied to the control gate electrodes depend on the channeltype, and can be independent of whether electrons or holes are stored inthe charge trapping layer, e.g., a memory material layer. For an n-dopedsemiconductor channel, all applied voltages can be reversed in polaritywith respect to the operation of a device employing a p-dopedsemiconductor channel. Thus, for an n-doped semiconductor channel a lowbias voltage (e.g. zero) can also be applied to the unselected controlgate to reduce read disturb in a device with an n-doped channel. Theregion from which charge carriers are repelled due to the electricalfield generated by the combination of the control gate bias voltageapplied to the selected control gate electrode 46-S and any storedelectrical charge in the at least one charge storage element 51 isherein referred to as a depleted channel portion 60D. The depth dd ofthe depleted channel portion 60D is a function of the control gate biasvoltage applied to the selected control gate electrode 46-S and thetotal amount of stored electrical charge in the at least one chargestorage element 51 in the selected level SL. If the depth dd of thedepleted channel portion 60D becomes equal to the channel thickness tc,which is the thickness, or the lateral dimension, of the semiconductorchannel 60, the semiconductor channel 60 becomes non-conducting.

In case the stored electrical charges in the at least one charge storageelement 51 are electrons, the depth dd of the depleted channel portion60D generally increases with an increase in magnitude of a negativevoltage applied to the selected control gate electrode 46-S and with thetotal amount of electrons stored in the at least one charge storageelement 51 in the selected level SL. Further, the depth dd of thedepleted channel portion 60D generally increases with a decrease inmagnitude in a positive voltage applied to the back gate electrode 68.Thus, by measuring the electrical current through the semiconductorchannel 60 under various combinations of control gate bias voltageapplied to the selected control gate electrode 46-S located at theselected level SL and the backside bias voltage applied to the back gateelectrode 68, the total amount of electrical charges stored in the atleast one charge storage element 51 at the selected level SL can bedetermined.

In an illustrative example, the unselect control gate bias voltageapplied to the unselected control gate electrodes 46-US can be in arange from 15 V to 30 V, although lesser and greater unselect controlgate bias voltages can also be employed. The backside bias voltageapplied to the back gate electrode 68 can be in a range from −2 V to 20V, although lesser and greater backside bias voltages can also beemployed. In one embodiment, the backside bias voltage applied to theback gate electrode 68 can be in a range from 2 V to 20V. In oneembodiment, the backside bias voltage applied to the back gate electrode68 can be in a range from 2 V to 15V. The control gate bias voltageapplied to the selected control gate electrode 46-S located at theselected level SL can be in a range from −2 V to −12 V, although lesserand greater control gate bias voltages can also be employed. The sourceline SL can biased, for example, at 0 V. The drain line DL can bebiased, for example, at a positive voltage selected from a range from0.2 V to 5.0 V.

Referring to FIG. 34, a set of bias voltage conditions is illustrated,which can be employed to determine the total amount of stored electricalcharge in a set of at least one memory element at a level within amemory stack structure. Each bias voltage condition includes a value forthe backside gate voltage V_BG that is applied to a back gate electrode,and a control gate bias voltage V_CGS that is applied to the selectedcontrol gate electrode that is adjacent to, and located at the samelevel as, the at least one charge storage element of which the totalamount of stored electrical charge is to be determined.

The points marked by “x” refer to exemplary electrical bias conditionsfor the combination of at least one of the plurality of electrical biasconditions can have a non-zero voltage for the value for the backsidebias voltage. In one embodiment, the polarity of the non-zero voltagefor the value for the backside bias voltage V_BS can be the oppositepolarity of a corresponding value for the control gate bias voltageV-CGS applied to the control gate electrode located at the selectedlevel SL. In one embodiment, the injected electrical charges cancomprise electrons, the non-zero voltage for the value for the backsidebias voltage V_BS can be a positive voltage, and the correspondingcontrol gate bias voltage V_CGS applied to the control gate electrodelocated at the selected level SL can be a negative voltage.

The distinction between a turn-on state of a semiconductor channel and aturn-off state of a semiconductor channel can be made employing apredefined level of electrical current, which is herein referred to as athreshold current level. The threshold current level can be selected tocoincide with the threshold value for the electrical current at which asensor circuitry configured to determine whether the semiconductorchannel is turned on or turned off generates a change in the output. Inother words, the threshold current level can be defined as the currentlevel at which the sensor circuitry generates a transition in theoutput.

For any fixed amount of electrical charges that are present in aselected set of at least one charge storage element, a set of electricalbias conditions at which the electrical current through thesemiconductor channel reaches the threshold current level can be definedby a curve in the graph. For a set of at least one charge storageelement configured to store a k-nary data, a total of k different curvescan be generated at which the electrical current through thesemiconductor channel reaches the threshold current level for apredefined bias voltage conditions between the source region and thedrain region.

For example, for a first state in which a first non-zero total amount ofstored electrical charges is present in the selected set of at least onecharge storage element, a first curve 701 can be plotted in a graphincluding the back gate voltage V_BG as one axis and the control gatevoltage V-CGS applied to the selected control gate electrode on theother axis. Similarly, for an i-th state in which an i-th non-zero totalamount of stored electrical charges is present in the selected set of atleast one charge storage element, an i-th curve (such as a second curve702 or a third curve 703) can be plotted in the same graph for eachvalue of i up to (k−1). For a zero total charge state in whichelectrical charges are not present, a k-th curve 700 can be plotted inthe same graph because application of a sufficiently high back gateelectrode voltage can turn on the semiconductor channel even if noelectrical charges are present in the selected set of at least onecharge storage element. While the various curves (700, 701, 702, 703)are illustrated as lines in FIG. 34, it is understood that the variouscurves (700, 701, 702, 703) may, or may not, be a straight line.Further, in case m control gate electrodes are located adjacent to theselected set of at least one charge storage element, a graph including(m+1) axes can be employed to plot an m-dimensional volume at which theelectrical current through the semiconductor channel reaches thethreshold current level for a predefined electrical bias conditionsbetween the source region and the drain region.

In order to determine in which charge state the selected set of at leastone charge storage element is in, a plurality of electrical biasconditions can be selected such that the plurality of electrical biasconditions include at least one point between each neighboring pair of kcurves representing the k different sets of electrical bias conditionsthat generate the threshold current level at a respective state of totalelectrical charges. A subset of electrical bias conditions under which arespective measured electrical current through the semiconductor channelis below a predefined threshold level can be identified based on theelectrical current measurements. The total amount of electrical chargestored in the set of at least one charge storage element can bedetermined based on the identified subset of electrical bias conditions.

For example, the electrical current through the semiconductor channelunder a predefined electrical bias voltage between the source region andthe drain region can be measured employing a two-dimensional matrix ofmeasurement conditions identified by the points marked “x.” If themeasured electrical current through the semiconductor channel is abovethe threshold current level in the subset SS of electrical biasconditions, and is below the threshold current level in the complementof the subset SS of electrical bias conditions, the total amount ofelectrical charges stored in the selected set of at least one chargestorage element is the amount of electrical charges corresponding tocurve 702, which can be the second non-zero total amount of storedelectrical charges for the selected set of at least one charge storageelement.

In one embodiment, the plurality of electrical bias conditions compriseselectrical bias conditions having different non-zero voltages for thevalue for the backside bias voltage V_BG and having a same value for thecontrol gate bias voltage V_CGS applied to the control gate electrodelocated at the selected level SL. In an illustrative example, theplurality of electrical bias conditions can comprise the set ofelectrical bias conditions corresponding to the points marked by “x” andlocated within the bidirectional arrow A.

In one embodiment, the total amount of electrical charge stored in theset of at least one charge storage element can be determined byidentifying a pair of electrical bias conditions (e.g., a1 and a2 inFIG. 34) having a same value for the control gate bias voltage V_CGSapplied to the control gate electrode located at the selected level SL,and having different values for the backside bias voltage V_BG appliedto the back gate electrode such that the electrical current through thesemiconductor channel is above the predefined threshold level for one ofthe pair of electrical bias conditions (e.g., a2), and is below thepredefined threshold level for another of the pair of electrical biasconditions (e.g., a1). The curve (e.g., 702) located between the twoelectrical bias conditions corresponds to the electrical charge storedin the set of at least one charge storage element (e.g., the secondnon-zero total amount of stored electrical charges out of k possiblecharge states). For a set of at least one charge storage elementconfigured to store a k-nary bit, in which k is an integer greater than1, at least (k−1) measurement conditions can be employed for theselected set of electrical bias conditions having different non-zerovoltages for the value for the backside bias voltage V_BG and having asame value for the control gate bias voltage V_CGS.

In one embodiment, the injected electrical charges can compriseelectrons, the non-zero voltage for the value for the backside biasvoltage V_BS can be positive for the plurality of electrical biasconditions, and electrical current through the semiconductor channelincreases with an increase in magnitude in the value for the backsidebias voltage V_BS within the plurality of electrical bias conditions. Inone embodiment, the order of the electrical bias conditions having thesame value for the control gate bias voltage V_CGS applied to thecontrol gate electrode located at the selected level SL within theselected set of measurement conditions (e.g., within the bidirectionalarrow A in FIG. 34) can be selected such that the applied value for thebackside bias voltage V_BG either increases sequentially, or decreasessequentially, between successive measurements. In this case, the appliedvalue for the backside bias voltage V-BS can be strictly increased, orstrictly decreased, an while a same control gate bias voltage V_CGS isapplied to the control gate electrode located at the selected level SL.As used herein, a “strict” increase refers to a positive increment overa pre-existing quantity, and a “strict” decrease refers to a decrease bya positive quantity (which is the same as an increase by a negativequantity) over a pre-existing quantity.

In one embodiment, the back gate voltage V_BS can be sequentiallyincreased, and a transition point value (e.g., the value at condition a2in an exemplary case of a second non-zero total amount of electricalcharges corresponding to the second curve 702) of the applied voltagefor the backside bias voltage V_GS can be identified when a cross-overabove the predefined threshold voltage occurs to determine the chargestate of the selected set of at least one charge storage element. Inanother embodiment, the back gate voltage V_BS can be sequentiallydecreased, and a transition point value (e.g., the value at condition a1in an exemplary case of a second non-zero total amount of electricalcharges corresponding to the second curve 702) of the applied voltagefor the backside bias voltage V_GS can be identified when a cross-overbelow the predefined threshold voltage occurs to determine the chargestate of the selected set of at least one charge storage element. In oneembodiment, the total amount of electrical charge stored in the set ofat least one charge storage element can be determined by a predefinedtable that correlates the transition point value to the total amount ofstored electrical charges.

In another embodiment, the total amount of electrical charge stored inthe set of at least one charge storage element can be determined byidentifying a pair of electrical bias conditions (e.g., b1 and a2 inFIG. 34) having different values for the control gate bias voltage V_CGSapplied to the control gate electrode located at the selected level SL,and having the same for the backside bias voltage V_BG applied to theback gate electrode such that the electrical current through thesemiconductor channel is above the predefined threshold level for one ofthe pair of electrical bias conditions (e.g., a2), and is below thepredefined threshold level for another of the pair of electrical biasconditions (e.g., b1). The curve (e.g., 702) located between the twoelectrical bias conditions corresponds to the electrical charge storedin the set of at least one charge storage element (e.g., the secondnon-zero total amount of stored electrical charges out of k possiblecharge states). For a set of at least one charge storage elementconfigured to store a k-nary bit, in which k is an integer greater than1, at least (k−1) measurement conditions can be employed for theselected set of electrical bias conditions having the same non-zerovoltage for the value for the backside bias voltage V_BG and havingdifferent values for the control gate bias voltage V_CGS.

In one embodiment, the injected electrical charges can compriseelectrons, the non-zero voltage for the value for the backside biasvoltage V_BS can be positive for the plurality of electrical biasconditions, and electrical current through the semiconductor channeldecreases with an increase in magnitude in the negative value for thecontrol gate bias voltage V_CGS within the plurality of electrical biasconditions. In one embodiment, the order of the electrical biasconditions having the same value for the back gate bias voltage V_BSwithin the selected set of measurement conditions (e.g., within thebidirectional arrow B in FIG. 34) can be selected such that the appliedvalue for the control gate bias voltage V_CGS (which is applied to thecontrol gate electrode located at the selected level SL) eitherincreases sequentially, or decreases sequentially, between successivemeasurements. In this case, the applied value for the control gate biasvoltage V_CGS can be strictly increased, or strictly decreased, while asame back gate bias voltage V_BS is applied to the back gate electrode.

In one embodiment, the control gate bias voltage V_CGS can besequentially increased (by becoming less negative or more positive), anda transition point value (e.g., the value at condition a2 within thebidirectional arrow B in an exemplary case of a second non-zero totalamount of electrical charges corresponding to the second curve 702) ofthe applied voltage for the control gate bias voltage V_CGS can beidentified when a cross-over above the predefined threshold voltageoccurs to determine the charge state of the selected set of at least onecharge storage element. In another embodiment, the control gate biasvoltage V_CGS can be sequentially decreased, and a transition pointvalue (e.g., the value at condition b1 within the bidirectional arrow Bin an exemplary case of a second non-zero total amount of electricalcharges corresponding to the second curve 702) of the applied voltagefor the control gate bias voltage V_CGS can be identified when across-over below the predefined threshold voltage occurs to determinethe charge state of the selected set of at least one charge storageelement. In one embodiment, the total amount of electrical charge storedin the set of at least one charge storage element can be determined by apredefined table that correlates the transition point value to the totalamount of stored electrical charges.

In general, identifying a charge state of a set of at least one chargestory element among possible k states can be effected by making (k−1)measurements at measurement conditions corresponding to intervalsbetween the (k−1) neighboring pairs of curves (701, 702, 703, 704)corresponding to the condition of threshold current level. In anillustrative example, a set of three electrical bias conditionsincluding a0, a1, and a2 within the bidirectional arrow A or a set ofthree electrical bias conditions including b0, b1, and a2 can beemployed to distinguish the charge state of a quaternary bit memory cellembodied in a set of at least one charge storage element.

The unselect control gate bias voltage that is applied to eachunselected control gate electrodes can be adjusted for each selectedvalue for the back gate bias voltage to ensure that the portions of thesemiconductor channel 60 located at any other level (i.e., theunselected levels USL) than the selected level SL belong to thenon-depleted channel portion. FIG. 35 illustrates the interdependencyfor optimal values for the backside bias voltage V_BS and unselectcontrol gate bias voltage V_CGU according to an embodiment of thepresent disclosure. While the graph in FIG. 35 illustrates a line, it isunderstood that the set of points including optimal combinations of thebackside bias voltage V-BS and the unselect control gate bias voltageV-CGU may, or may not, be on a straight line.

Referring collectively to FIGS. 9A, 9B, 30A, 30B, 31, 34 and 35, athree-dimensional NAND string is provided, which includes asemiconductor channel (160 or 60) having at least one vertical portion,a plurality of vertically separated control gate electrodes (as embodiedin electrically conductive layers 46), a memory film 50 located betweena first side of the vertical portion of the semiconductor channel (160or 60) and the control gate electrodes, a back gate electrode (168 or68), and a back gate dielectric (166 or 66) located between a secondside of the vertical portion of the semiconductor channel (160 or 60)and the back gate electrode (168 or 68). The three-dimensional NANDstring can be operated by applying a positive voltage to the back gateelectrode (168 or 68) and by applying a negative read voltage to aselected control gate electrode (as embodied by an electricallyconductive layer 46) to read a selected cell of the NAND string. Avoltage can be applied between a source (such as source region 30) and adrain (such as drain region (63 or 163) of the NAND string.

During the read operation of the NAND string, it can be determined thatcharge is stored in a charge storage region of the memory film 50 of theselected cell if no current flows between the source and the drainduring application of the positive voltage to the back gate electrode(68 or 168) and the negative read voltage of the selected control gateelectrode. Further, it can be determined that no charge is stored in acharge storage region of the memory film of the selected cell if currentflows between the source and the drain during application of thepositive voltage to the back gate electrode and the negative readvoltage of the selected control gate electrode.

In one embodiment, a first pair of electrical bias conditions can beapplied, which includes applying a first backside bias voltage to theback gate electrode and a first control gate bias voltage to the controlgate electrode of the selected cell. Subsequently, a second pair ofelectrical bias conditions can be applied, which includes applying asecond backside bias voltage to the back gate electrode and a secondcontrol gate bias voltage to the control gate electrode of the selectedcell. The first pair of electoral bias conditions and the second pair ofelectrical bias conditions can be applied sequentially. In oneembodiment, the first and the second backside bias voltages can be thesame and the first and the second control gate bias voltages can bedifferent. Alternatively, the first and the second backside biasvoltages can be different and the first and the second control gate biasvoltages can be the same. A total amount of electrical charge stored ina charge storage region of the memory film of the selected cell can bedetermined when an electrical current through the semiconductor channel(60 or 160) is above a predefined threshold level for the first pair ofelectrical bias conditions, and is below a predefined threshold levelfor the second pair of electrical bias conditions. In one embodiment, anabsolute value of the positive voltage applied to the back gateelectrode can be smaller than an absolute value of the negative readvoltage applied to the selected control gate electrode. In oneembodiment, the back gate electrodes (68 or 168) can be employed to turnon the backside of the semiconductor channel (60 or 160) and increasethe cell current without increasing the leakage current through thefront side (i.e., the outer side) of the semiconductor channel (60 or160).

The programming and measurement methods of the present disclosure can beemployed in conjunction with a three-dimensional memory device asembodied in any of the first, second, and third exemplary structures. Inan illustrative example, the a three-dimensional memory device caninclude a trench extending through an alternating stack (32, 142) andincluding a first sidewall and a second sidewall that are laterallyspaced from each other, a plurality of semiconductor strip structures160 straddling the trench, and a back gate dielectric 168 contactinginner sidewalls of the plurality of semiconductor strip structures as inthe first and second exemplary structures illustrated in FIGS. 9A, 9B,18A, and 18B. Each semiconductor strip structure 160 can contact arespective portion of the first sidewall and a respective portion of thesecond sidewall, and can be laterally spaced from one another. Each ofthe plurality of semiconductor strip structures 160 can include at leastone semiconductor channel. The back gate electrode 168 can contact innersidewalls of a back gate dielectric 166. Each semiconductor channel canbe electrically isolated from the substrate 10 by a memory film 50 as inthe first exemplary structure. Alternatively, each of the plurality ofsemiconductor strip structures 160 can be electrically shorted to asource line layer 12 located within the substrate 10 as in the secondexemplary structure.

In another illustrative example, the three-dimensional memory device canfurther comprise a pillar structure (68, 66, 60, 63, 30, 50) locatedwithin a memory opening extending through the alternating stack (32, 46)as in the third exemplary structure illustrated in FIGS. 30A and 30B.The pillar structure (68, 66, 60, 63, 30, 50) can comprise a back gateelectrode 68 and a set of nested layers laterally surrounding the backgate electrode 68. The set of nested layers can include, from inside tooutside, a back gate dielectric 66, the semiconductor channel 60, and amemory film 50.

Although the foregoing refers to particular preferred embodiments, itwill be understood that the disclosure is not so limited. It will occurto those of ordinary skill in the art that various modifications may bemade to the disclosed embodiments and that such modifications areintended to be within the scope of the disclosure. Where an embodimentemploying a particular structure and/or configuration is illustrated inthe present disclosure, it is understood that the present disclosure maybe practiced with any other compatible structures and/or configurationsthat are functionally equivalent provided that such substitutions arenot explicitly forbidden or otherwise known to be impossible to one ofordinary skill in the art. All of the publications, patent applicationsand patents cited herein are incorporated herein by reference in theirentirety.

What is claimed is:
 1. A monolithic three-dimensional memory device,comprising: a stack including an alternating plurality of insulatorlayers and electrically conductive layers and located over a top surfaceof a substrate; an opening extending through the stack; a memory filmlocated in the opening; at least one semiconductor channel located overthe memory film in the opening, such that at least a portion of the atleast one semiconductor channel extends substantially perpendicular tothe top surface of the substrate; a back gate dielectric located overthe at least one semiconductor channel in the opening; and a back gateelectrode located over the back gate dielectric in the opening.
 2. Themonolithic three-dimensional memory device of claim 1, wherein: thedevice comprises a vertical NAND device located in a device region; andat least one of the electrically conductive layers in the stackcomprises, or is electrically connected to, a word line of the NANDdevice.
 3. The monolithic three-dimensional memory device of claim 2,wherein: the opening comprises a trench including a first sidewall and asecond sidewall that are laterally spaced from each other; the memoryfilm is located on the first sidewall, on the second sidewall, and overthe top surface of the substrate; the at least one semiconductor channelcomprises a plurality of semiconductor strip structures straddling thetrench, wherein each semiconductor strip structure is located over arespective portion of the first sidewall and a respective portion of thesecond sidewall, and the strip structures are laterally spaced from oneanother; the dielectric contacts inner sidewalls of the plurality ofsemiconductor strip structures; and the back gate electrode contactsinner sidewalls of the back gate dielectric.
 4. The monolithicthree-dimensional memory device of claim 3, wherein the memory filmcomprises a tunneling dielectric in contact with at least one of theplurality of semiconductor strip structures, a blocking dielectric, andat least one charge storage region selected from a charge trapping layerand floating gate material portions located between the tunnelingdielectric and the blocking dielectric.
 5. The monolithicthree-dimensional memory device of claim 3, wherein: the back gatedielectric straddles at least two of the plurality of semiconductorstrip structures; and the back gate electrode straddles at least two ofthe plurality of semiconductor strip structures.
 6. The monolithicthree-dimensional memory device of claim 3, wherein each of theplurality of semiconductor strip structures includes a respective firsthorizontal portion located over the stack and a respective secondhorizontal portion located at a bottom portion of the trench.
 7. Themonolithic three-dimensional memory device of claim 6, wherein each ofthe plurality of semiconductor strip structures further includes: arespective first vertical portion adjoined to the respective firsthorizontal portion and the respective second horizontal portion; and arespective second vertical portion adjoined to a respective thirdhorizontal portion located over the stack and the respective secondhorizontal portion.
 8. The monolithic three-dimensional memory device ofclaim 3, wherein: the trench laterally extends along a first horizontaldirection; and each of the plurality of semiconductor strip structureslaterally extends along a second horizontal direction that is differentfrom the first horizontal direction.
 9. The monolithic three-dimensionalmemory device of claim 8, wherein each of the plurality of semiconductorstrip structures has a respective uniform width along the secondhorizontal direction.
 10. The monolithic three-dimensional memory deviceof claim 3, wherein each of the plurality of semiconductor stripstructures is electrically isolated from the substrate by a memory film.11. The monolithic three-dimensional memory device of claim 3, whereineach of the plurality of semiconductor strip structures is electricallyshorted to a source line layer located within the substrate.
 12. Themonolithic three-dimensional memory device of claim 2, wherein: theopening comprises a memory opening; the at least one semiconductorchannel comprises a pillar shaped semiconductor channel located in thememory opening; and a pillar structure is located within the memoryopening and comprising the back gate electrode and a set of nestedlayers laterally surrounding the back gate electrode, wherein the set ofnested layers include, from inside to outside, the back gate dielectric,the semiconductor channel, and at least a portion of the memory film.13. The monolithic three-dimensional memory device of claim 12, furthercomprising a patterned conductive material layer contacting a bottomsurface of the back gate electrode and electrically isolated from thesemiconductor channel.
 14. The monolithic three-dimensional memorydevice of claim 13, wherein the patterned conductive material layercontacts a bottom surface of another back gate electrode located withinanother memory opening through the stack.
 15. The monolithicthree-dimensional memory device of claim 13, further comprising adielectric material portion embedded within an upper portion of thesubstrate and contacting a bottom surface of the patterned conductivematerial layer.
 16. The monolithic three-dimensional memory device ofclaim 12, further comprising: a dielectric cap portion contacting a topsurface of the back gate electrode; and a drain region contacting a topsurface of the semiconductor channel and a surface of the dielectric capportion.
 17. The monolithic three-dimensional memory device of claim 12,further comprising a source region adjoined to a bottom portion of thesemiconductor channel.
 18. The monolithic three-dimensional memorydevice of claim 17, further comprising a source electrode contacting,and laterally surrounding, the source region, and located over thesubstrate.
 19. The monolithic three-dimensional memory device of claim18, wherein: the source region laterally surrounds a portion of the backgate dielectric; the source electrode underlies the stack; and abackside contact via structure extends through the stack and contactsthe source electrode.
 20. The monolithic three-dimensional memory deviceof claim 19, further comprising an annular dielectric material portionhaving a same composition as the memory film and contacting an outersidewall of the back gate dielectric under at least one of the sourceregion and the source electrode.
 21. The monolithic three-dimensionalmemory device of claim 17, wherein the source region has a samehorizontal cross-sectional shape as the semiconductor channel, and islaterally spaced from the back gate electrode by the back gatedielectric.
 22. The monolithic three-dimensional memory device of claim2, further comprising: a stepped word line connection region locatedadjacent to the device region; a plurality of word line contact viastructures contacting respective word lines in the word line connectionregion; a conductive layer located under the stack and contacting theback gate electrode; and a back gate contact via structure contactingthe conductive layer in the word line connection region.
 23. Themonolithic three-dimensional memory device of claim 2, wherein: nocharge storage region is present between the back gate electrode and theat least one semiconductor channel; the NAND device comprises: aplurality of semiconductor channels, wherein at least one end portion ofeach of the plurality of semiconductor channels extends substantiallyperpendicular to a top surface of the semiconductor substrate; aplurality of charge storage elements, each charge storage elementlocated adjacent to a respective one of the plurality of semiconductorchannels; and a plurality of control gate electrodes having a stripshape extending substantially parallel to the top surface of thesubstrate; the plurality of control gate electrodes comprise at least afirst control gate electrode located in the first device level and asecond control gate electrode located in the second device level; theelectrically conductive portions in the stack comprise, or are inelectrical contact with, the plurality of control gate electrodes andextend from the device region to a contact region containing theplurality of electrically conductive via connections; and the substratecomprises a silicon substrate containing a driver circuit for the NANDdevice.
 24. A method of manufacturing a monolithic three-dimensionalmemory device, comprising: forming a stack including an alternatingplurality of first material layers and second material layers over asubstrate; forming an opening that vertically extends through the stack;forming a memory film over at least one sidewall of the opening; formingat least one semiconductor channel in the opening; forming a back gatedielectric on inner sidewall of the at least one semiconductor channel;and forming a back gate electrode on inner sidewall of the back gatedielectric.
 25. The method of claim 24, wherein: the opening comprises atrench that vertically extends through the stack and laterally extendsalong a first horizontal direction; the least one channel comprises aplurality of semiconductor strip structures straddling the trench andextending along a second horizontal direction that is different from thefirst horizontal direction; the back gate dielectric is formed on innersidewalls of the plurality of semiconductor strip structures; and theback gate electrode is formed on inner sidewalls of the back gatedielectric.
 26. The method of claim 25, wherein the memory film isformed on sidewalls of the trench and over a top surface of thesubstrate.
 27. The method of claim 26, wherein: forming the memory filmcomprises forming a tunneling dielectric and at least one charge storageregion; and at least one of the plurality of semiconductor stripstructures is formed directly on the tunneling dielectric.
 28. Themethod of claim 25, wherein forming the plurality of semiconductor stripstructures comprises: forming a semiconductor material layer over thestack and on sidewalls of the trench; and patterning the semiconductormaterial layer into the semiconductor strip structures that arelaterally spaced apart from one another.
 29. The method of claim 25,wherein: the back gate dielectric extends along the first horizontaldirection within the trench and contacts surfaces of at least two of theplurality of semiconductor strip structures; and the back gate electrodeextends along the first horizontal direction within the trench andstraddles the at least two of the plurality of semiconductor stripstructures.
 30. The method of claim 25, further comprising: forming thememory film as a plurality of contiguous material layers within thetrench; patterning one layer among the plurality of contiguous materiallayers with a same pattern as the plurality of semiconductor stripstructures employing another layer among the plurality of contiguousmaterial layers as an etch stop layer.
 31. The method of claim 25,wherein the memory film is formed on a bottom surface of the trench,wherein the plurality of semiconductor strip structures is formed over ahorizontal portion of the memory film and is electrically isolated fromthe substrate by the horizontal portion of the memory film.
 32. Themethod of claim 25, further comprising forming an opening through thememory film by removing a horizontal portion of the memory film over thebottom surface of the trench, wherein the plurality of semiconductorstrip structures contacts the substrate through the opening in thememory film.
 33. The method of claim 24, wherein: the opening comprisesa memory opening; and the at least one channel comprises a semiconductorchannel.
 34. The method of claim 33, further comprising forming apatterned conductive material layer over the substrate, wherein the backgate dielectric and the back gate electrode are formed directly on a topsurface of the patterned conductive material layer.
 35. The method ofclaim 33, wherein the semiconductor channel is formed by: depositing asemiconductor channel layer; and removing a horizontal portion of thesemiconductor channel layer over a bottom surface of the memory opening,wherein an opening is formed in the memory film.
 36. The method of claim33, wherein the back gate dielectric is formed by: depositing a backgate dielectric layer in the memory opening and over the stack; andanisotropically etching the back gate dielectric layer to form anopening through a horizontal portion of the back gate dielectric layerwithin the memory opening, wherein a remaining vertical portion of theback gate dielectric layer constitutes the back gate dielectric.
 37. Themethod of claim 33, wherein the back gate electrode is formed by:depositing a conductive material within a cavity laterally enclosed bythe back gate dielectric; and recessing a top surface of the depositedconductive material to a height that is located below a horizontal planeincluding a top surface of the stack.
 38. The method of claim 33,further comprising forming a drain region in contact with an upperportion of the semiconductor channel.
 39. The method of claim 38,further comprising: converting bottom portion of the semiconductorchannel to a source region by introducing dopants through a sidewall ofthe bottom portion of the semiconductor channel; and forming a sourceelectrode directly on the source region and a remaining portion of thememory film, wherein the source electrode laterally surrounds the sourceregion.
 40. The method of claim 24, further comprising: forming a backside opening in the stack; removing the second material layers throughthe back side opening to form back side recesses between the firstmaterial layers which comprise insulating layer; and forming controlgate electrodes in the back side recesses through the back side openingto form a vertical NAND device.